Help me solve errors in VHDL code

i'm a beginer in VHDL, when i wrote this code, it generated some errors, can somebody help me?
ERROR:HDLParsers:164 - "D:/Chinh/FPGA/lab/traffic/STAT_MAC.vhd" Line 40. parse error, unexpected TICK
ERROR:HDLParsers:164 - "D:/Chinh/FPGA/lab/traffic/STAT_MAC.vhd" Line 45. parse error, unexpected TICK
ERROR:HDLParsers:164 - "D:/Chinh/FPGA/lab/traffic/STAT_MAC.vhd" Line 51. parse error, unexpected TICK
ERROR:HDLParsers:164 - "D:/Chinh/FPGA/lab/traffic/STAT_MAC.vhd" Line 55. parse error, unexpected TICK



LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;




ENTITY STAT_MAC IS
PORT (CLK,RESET: IN std_logic;
TIMER : in std_logic_vector ( 3 downto 0);
AMB, GRN, RD : out std_logic);


END STAT_MAC;

ARCHITECTURE BEHAVIOR OF STAT_MAC IS
-- State variables for machine sreg
-- SIGNAL AMBER, next_AMBER, GREEN, next_GREEN, RED, next_RED, REDAMB,
-- next_REDAMB : std_logic;
SIGNAL next_AMB,next_GRN,next_RD : std_logic;
signal tmr : std_logic_vector (3 downto 0);
BEGIN
p00: PROCESS (CLK,next_AMB,next_GRN, next_RD)
BEGIN
IF CLK='1' AND CLK'event THEN
AMB <= next_AMB;
GRN <= next_GRN;
RD <= next_RD;
END IF;
END PROCESS;
p01 : process (TIMER)
begin
if ((TIMER = '0100' or TIMER = '0101' or TIMER = '0110' or TIMER = '0111' or
TIMER = '1100' or TIMER = '1101' or TIMER = '1110' or TIMER = '1111') and RESET = '0') then
next_AMB <= '1';
ELSE next_AMB <= '0';
END IF;
if ((TIMER = '0000' or TIMER = '0001' or TIMER = '0010' or TIMER = '0011' or
TIMER = '0100' or TIMER = '0101' or TIMER = '0110' or TIMER = '0111') and RESET = '0' ) then
next_RD <= '1';
else next_RD <= '0';
end if;

IF ((TIMER = '1000' or TIMER = '1001' or TIMER = '1010' or TIMER = '1011' )and RESET = '0') then
next_GRN <='1';
ELSE next_GRN <='0';
END IF;
if RESET = '1' then TIMER <= '0000'; end if;
end process;

END BEHAVIOR;


i wote it in XINLINX ISE 10.1

Re: help me VHDL code

Just about the syntax problem:

You use '0000' (with single quotes). This is not correct. This should be double quotes, like "0000".

For a std_logic_vector -> use "" (double quotes)
For a std_logic -> use '' (single quotes)

Keep in mind that there is a difference between "0" and '0' -> the first is a std_logic_vector (made of a single bit), and the second a std_logic (also a single bit). Since a std_logic is always a single bit, you will never see more than a single character within single quotes.

Added after 14 minutes:

Just one hint (since you will see that your code will not compile):

TIMER is defined as an input in your entity.
In the second process you want to assign a value to TIMER (based on RESET). This is not possible (TIMER being an input).
If TIMER is a signal, then you could do this, but not when it is an entity input.

This is typically handled like follows:

1. define a signal
signal tm: std_logic_vector(3 downto 0);

2. (outside a process, unless you want a synchronous reset) assign the entity signal to your signal
tmr <= TIMER when (RESET = '1')
else
"0000";

3. Use 'tmr' anywhere TIMER is used

From what I can see you where about to do this ... (having degined tmr)