VCD vectors to WGL (tester) format conversion - here's how !

I need some experienced hints as to how generate WGL formatted vectors from VCD vectors (that latter was generated from a functional NC-Sim simulation) ?

Notes:
1. I have acces to both Synopsys 'TetraMax' and Mentor DFTAdvisor (+FastScan), but have no practical experience with neither tool.
2. I try 'set patterns external' (in TetraMax CMD command-line BUILD > prompt), but I get a Warning: "Incorrect mode".

Please help.


====================


Edit: finally resolved, see below ...

VCD vectors to WGL (tester) format conversion

After digging into Mentor's "FlexTest" I managed to do it, here's the flow:
[ all "//" delimiters are notes delimiters ... ]


1. Edit a VCD read control file ("vcd_control.scr"). In my case, a 500nS test cycle, it looks something like this (note that the units below MUST comply with units as written in the VCD file - in my case it is in 1pS):
-------------
set collision check off
add timeplate tp 500000 10000 0 // set timeplate (and sample point) for all inputs
add timeplate tp_clk 500000 260000 250000 250000 // set timeplate for clock = CLK
setup input waveform tp
add input waveform tp_clk CLK
setup output strobe 260000 // set sample point for all outputs
set time check time_check.txt // report timing checks
-------------

2. Edit a 'timeplate' procedure file ("timeplate_proc.txt"). In my case, it looks something like this:
-------------
// Set the base time increment for use in all timeplates
set time scale 1.0 ns;

// Define the strobe time for the measure statements
//set strobe_window time 1;

timeplate tp_def =
force_pi 0;
bidi_force_pi 0;
measure_po 250;
bidi_measure_po 250;
pulse CLK 250 250;
period 500;
end;
-------------

3. Import the gate-level design (if necessary, translate the gates models to Mentor's own - using 'libconv' tool). It is also assumed that an eVCD [or VCD] functional print-on-change vector file has already been generated ("vectors.vcd" in the following commands).


4. Perform the following comands in 'FlexTest':
--------------
set hypertrophic limit off
set test cycle 2 // 2 timeframes in 1 test cycle
setup pin constraint NR 1 0 // assert all inputs at clock negedge
add pin constraints CLK SR1 1 0 1 // CLK neg RZ (SR1 - not always, R1 - always)
setup pin strobe 1 // sample all outputs at clock posedge
set sys m g // go from FlexTest SETUP mode to GOOD mode
set pattern source external vectors.vcd -vcd -c vcd_control.scr // read eVCD file

save pat vectors.wgl -wgl -re -ext -cyc timeplate_proc.txt -procfile // write a WGL file - cycle tests patterns

or
[
read procfile timeplate_proc.txt
save pat vectors.wgl -wgl -re -ext -cyc
]
--------------

5. The result, "vectors.wgl" file, is in the desired cycle-based WGL format.