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How to determine number of clock/global lines using Xilinx?

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cafukarfoo

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Hi all,

Can anyone share how to determine number of clock/global lines using Xilinx ISE software?

I am looking at the pinout report. I saw there is some pin name named *GCLK* and *CHCLK*. Is this pin the clock/global lines?

Thanks.
 

Can you tell me exactly what you are looking for?
Xilinx FPGAs has internal GLOBAL routing lines .
There are certain pins dedicated to connect clock ( xtal) to the FPGA. You can see those in FPGA editor . If you are using ISE11+ then use PlanAhead.
 

Re: How to determine number of clock/global lines using Xili

Hi Palai,

I am looking into pin which is dedicated for clock/global lines.

Because i am using external clock. So i want to make sure i assign the clock to the right pin.

I am looking at the pinout report. I saw there is some pin name named *GCLK* and *CHCLK*. Is this pin the clock/global lines?

THanks.
 

GCLK pins are the "Global clock pins" you can feed an external clock signal to FPGA using these pins , both in single ended and differential modes.


Ex. In xilinx ML555 board a 30 MHz clock input is used on GCLK pin(L19).
Once the clock signal is inside the FPGA you can used BUFG and pass it to DCM and then to the design.
 

Re: How to determine number of clock/global lines using Xili

Hi Palai,

By referring to the example given by you,
why can't it direct assign the GCLK pin to DCM instead?

If i need to go through BUFG, how can i do that in Xilinx?

Thanks.

Ex. In xilinx ML555 board a 30 MHz clock input is used on GCLK pin(L19).
Once the clock signal is inside the FPGA you can used BUFG and pass it to DCM and then to the design.
 

why can't it direct assign the GCLK pin to DCM instead?
You can connect it directly . but to do that you have to instanciate the DCM primitive in your code and connectt he pin. On the other hand if you use the architecture wizzard , it will instantiate an IBUFG in between your GCLK pin and the DCM clk input port.
Anyway xilinx recomends to use BUFG.
Matter of fact we all want our clock signal to be clean and stable and should be capable of driving lot .

If i need to go through BUFG, how can i do that in Xilinx?
As i mentioned earlier . just use xilinx coregen and got to fpga features and design then clock , select the device you are using spartan/ virtex. then choose the appropriate DCM/PLL.
 

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    cafukarfoo

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