cafukarfoo
Full Member level 3
Hi Sir/Madam,
Can someone share their method to avoid
reg/wire bus optimization during FPGA synthesis?
I want to maintain some of the reg/wire bus so that i can view the result using SignalTap/Chipscope software.
Thanks in advance for your help.
Can someone share their method to avoid
reg/wire bus optimization during FPGA synthesis?
I want to maintain some of the reg/wire bus so that i can view the result using SignalTap/Chipscope software.
Thanks in advance for your help.