Adding IOs in SOC Encounter

soc encounter.pdf

How to insert pad ring in SOCE? Is it usually done by editing the netlist manually to include IO cells in the gate level netlist before import it to the Encounter? Is the location of the pads in SOCE also manually adjusted? How about the routing of supply and gnd among IOs? How to add fill io pads and clamp cells?

If some one can provide an example of SOCE script that does the pad ring insertion, then it will be very helpful.

Thanks.

reading in a def file in encounter

Hi,
Actually, you need paste only signal io instances into netlist. It should be done to get actual timing. Evently, you donot need to paste Supply/Cut/Filler/Decap ios into netlist as SOC does it automaticaly during DEF/io_file reading.
So, You have two way to include io pad ring into Encounter:
1. reading DEF file (you should have DEF file already)
2. reading IO Assignment file (you should have IO file already)

I usually create IO file manually basing on packaging rules (any way, packaging engineer should provide you IO ring specification: which pads on which side). Io file syntax is extremely simple (look page96 of soceUG.pdf).

soc encounter

in the encounter install directory: ~/share/fe/gift/script/ (i am not so sure, but like this) , or the cadence workshop in install directory which called dtmf: you can find some script as you want.

pad ring routing created 0 new wires

You guys are very helpful.

Will the power/ground ring wires automatically routed by sroute? Or maybe all the IOs are connected and form a ring by their placement and any gap is filled with filler IOs? I did a sroute and notice that there is nothing done to the IO cells, and I don't see the gap being filled with fillers.

Thanks.

addring encounter

ebuddy said:

You guys are very helpful.

Will the power/ground ring wires automatically routed by sroute? Or maybe all the IOs are connected and form a ring by their placement and any gap is filled with filler IOs? I did a sroute and notice that there is nothing done to the IO cells, and I don't see the gap being filled with fillers.

Thanks.

Click to expand...

my understanding is that you have to add the IO fillers via a command prior
to routing. sroute will connect the power rings to the power pads, fix unconnected
stripes and also connect std cell power pins to global power lines.

Hi,
when you talk about 'ring' you should specify which ring you mean: pad ring (metall wires which sypply of IO cells rather then core cell) or Core ring (metall rings that sypply core std cells)
If you talk about Pad ring, you should clearly understand of your IO library, some of libraries contain segments of pad ring metal and pins for abutment, some of libraries do not. In case if your IO library does not require pad ring routing, you need only to fill all windows in you io ring to avoid any discountinious (gaps). So, when you will dump GDS you should see discountinous metal rings over whole io ring (please donot forget to paste io corner cells).
In case if you IO library requires pad ring routing, it is not a problem as S-route allows to do it easily and painless.

You should understand that s-route can connent some prepeared Power Structures (such as Core ring, Block rings, Stripes and etc) but cannot create them.
If you are interested I could attach my last project scripts:
snapRoute
source SCRIPTS/createDDLRing.tcl
source SCRIPTS/createPLLRing.tcl
source SCRIPTS/routePLL.tcl
source SCRIPTS/createCoreRing.tcl
source SCRIPTS/routeCoreRing.tcl
## split all IO wires
#source SCRIPTS/splitIOWires.tcl
source SCRIPTS/createCoreStripes.tcl
source SCRIPTS/routeCore.tcl