Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Hierarchical Flow Vs Flatten Flow

Status
Not open for further replies.

kumar_eee

Advanced Member level 3
Advanced Member level 3
Joined
Sep 22, 2004
Messages
814
Helped
139
Reputation
276
Reaction score
113
Trophy points
1,323
Location
Bangalore,India
Activity points
4,677
hierarchical flow

What is meant by Hierarchical Flow & Flatten flow?. How it differs from each other?.
 

Hi,
Simplest explanation:
Flat flow - the whole P&R design is created as 1 module
Hierarchical - P&R design is partitioned into different modules, hence, multiple modules can be worked on at 1 time
Is this enough?
 

    kumar_eee

    Points: 2
    Helpful Answer Positive Rating
hi kumar,
lets take a example of a multi cpu processor (2) implementation example
in flat , all the cpus (2) RTL is taken as one module and implemented at a time,
in hierarchical , each cpu implemented seperatly and all the models are extracted and instantiated at the top level as a macros,
hope its clear
 

    kumar_eee

    Points: 2
    Helpful Answer Positive Rating
Hi,
Could you please elaborate on the advantages of each flow?
When do we opt for flat flow?
Which flow consumes less memory, and faster?
If a design is flattened, what are the changes in the design?
How do the constraints change?
Actually there are lot more things that can be discussed on flattening.
Can anybody help me?

Thanks,
Sowmya
 

hi

flat is good to adopt if design size is smaller, as design size increase tools calibre to handle the various aspects decreases, we have seen improve ment in QoR and run time for big designs using hier flow, but its not worth doing a hierarchical flow for smaller designs.
hier flow consumes less memory and faster, if design is flattened, then u may end up requireing large machiens (many cpus), huge turnaround time,
need to genreate i/o constraints for each block of hierarchial design and top level constraints wont change

we have done lot of experiments and presentations in various conferencess like snug & cdn live, hoep u can find more information there also
 

Hi Raju,
Thank you for your reply.
It would be great if you can upload the related docs.

Thanks,
Sowmya
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top