homer2k1
Newbie level 5
set_dont_touch on cell
I used Module Compiler to create some fast adders. How can I tell Design Compiler not to change them?
Say I have two instances of this module, adderInst1 and adderInst2. I've tried using "set_dont_touch adderInst1" which works for just one instance, but how do I use * to match every instance? I would rather embed the "set_dont_touch" command in the Verilog netlist for the adder itself. Is there a way to do this?
I used Module Compiler to create some fast adders. How can I tell Design Compiler not to change them?
Say I have two instances of this module, adderInst1 and adderInst2. I've tried using "set_dont_touch adderInst1" which works for just one instance, but how do I use * to match every instance? I would rather embed the "set_dont_touch" command in the Verilog netlist for the adder itself. Is there a way to do this?