How do you know where to add the clock gate in the design?

How do you know where to add the clock gate in the design?. What are the basic criteria that are followed while adding the clock gate in the design?.

20:45 clock

Clock gating can be added manually into the RTL (based on architecture definition) or automatically by synthesis tool.

ex.
In an SOC you can have your clock generation module create a separately gated clock for each IP on your chip. Just have a programmable register in you clock module to allow you to turn each clock on/off separately.

ex2.
synthesis tool can be allowed to add clock gating automatically. The common case is for enable signals like below. You can define minimum number of registers to be gated automatically so you do not get clock gating cells gating single registers.

always @(posedge clk)
if (rst)
regA <= 1'b0;
else if (enable)
regA <= signalB;
end

this can be synthesized into:
1) a flop with a mux in front of the D pin controlled by enable, one input is signalB the other is output Q of flop
2) a flop with a clock gating cell controlled by enable. Now if regA is 32 bits wide, it would make sense to choose this option. The clock gating cell would be pushed up the clock tree, stopping some of the clock buffers from toggling when enable is low.

clock gating

nice explanation shelby, just adding to these,, generally tool will be adding clock gates where bunch of mux-register pair has common enable, mostly tools scope will be limited to a single hierarchy, and u can disable this defualut behaviour,,, by ckgating u get dynamic power and area advantage at the cost of speed

clock gate

I agree with you guys that it will save the dynamic power dissipation.. But, How do you come up with What kind of portion/numbers that you want to turn off when not in use?.

Lets say I have 50 registers in my design, now the qstn is How do you know where to insert the clock gate & How do you group the registers?.

clock gate and flop grouping

hi kumar,
EDA tools can come up with best possible number of reg to be combined, and just we need to say the max and min bandwidth, and one more thing, if enable signal is same then only these regs can be merged if not they can;t.
and my exp says that min &max bandwidth limit will come from trials only

Added after 49 seconds:

merging i mean,, can be clked from a single clk gate