RAM access problem in verilog [50 to 100 points on solution]

ram with verylog

Hi friends,
I have modeled RAM in verilog. The code is simple see below. I can read and write it without any problem. When i try to access it from the test bench using a new instance, i get xxxxxxxxxxxxxxxxx. Can anyone guide me towards the solution.
Note that i have to access RAM in different module of a larger project and i have to create RAM instances to access RAM.

The one who helps get 50 to 100 points.


timescale 1ns / 1ps

module REGFILE(
output reg [127:0] Rdata,
input [127:0] Wdata,
input clk,
input Read,
input Write
);


reg [127:0] RAM;

always @(posedge clk,Read,Write)
if(Read)
begin
Rdata = RAM;
end
else if (Write)
begin
RAM = Wdata;
end


endmodule







/***********************************************Test Bench ********/
`timescale 1ns / 10ps


module test;


reg clk;
reg Read, Write;
reg Read1, Write2;
reg [127:0] X;

wire [127:0] Y;
wire [127:0] Z;


initial
begin

clk = 0;
X = 128'b0;

end



always
begin
#5 clk = ~clk;
end



initial
#15 Write = 1;
initial
#25 Write = 0; //stop writing

initial
begin #25 Read = 1; Read1 = 1; end

initial
begin #35 Read = 0; Read1 = 0; end


REGFILE u0(.Rdata(Y),
.Wdata(X),
.clk(clk),
.Read(Read),
.Write(Write)
);

REGFILE u1(.Rdata(Z),
.Wdata(X),
.clk(clk),
.Read(Read1),
.Write(Write1)
);


initial
$monitor($time,",X is %h, Y is %h, Z is %h Read is %d, Write is %d \n",X,Y,Z,Read,Write);

endmodule






/**************** Simulation Result **********************************/


# 0,X is 00000000000000000000000000000000, Y is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, Z is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Read is x, Write is x
#
# 15,X is 00000000000000000000000000000000, Y is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, Z is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Read is x, Write is 1
#
# 25,X is 00000000000000000000000000000000, Y is 00000000000000000000000000000000, Z is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Read is 1, Write is 0
#
# 35,X is 00000000000000000000000000000000, Y is 00000000000000000000000000000000, Z is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Read is 0, Write is 0

verilog access index

Input is X, 0000000000000000000000

Regfile u0 gets a write signal to write this value in, and you can read it out. Y is 0000000 after the operation.

Regfile u1 is never written to. The write signal here, Write1 is never declared or change. So Regfile u1 is uninitialized.... when you read from an uninitialized Regfile, you should get Z=xxxxxxxxxxxxxxxxxxxxxx.

verilog ram module code read write same time

timescale 1ns / 1ps

module REGFILE(
output reg [127:0] Rdata,
input [127:0] Wdata,
input clk,
input Read,
input Write
);

reg [127:0] RAM;

always @(posedge clk)
if(Read)
begin
Rdata = RAM;
end
else if (Write)
begin
RAM = Wdata;
end

endmodule

`timescale 1ns / 1ps

module test;

reg clk;
reg Read, Write;
reg Read1, Write1;
reg [127:0] X;

wire [127:0] Y;
wire [127:0] Z;


initial
begin

clk = 0;
X = 128'b0;
write = 0;
write1 = 0;
read = 0;
read1 = 0;
#15 write = 1;
write1 = 1;
#10 write = 0;
write1 = 0;
read = 1;
read1 = 1;
#10 read = 0;
read1=0;

X = {128{1'b1}};
#15 write = 1;
write1 = 1;
#10 write = 0;
write1 = 0;
read = 1;
read1 = 1;
#10 read = 0;
read1=0;
end



always
begin
#5 clk = ~clk;
end

REGFILE u0(.Rdata(Y),
.Wdata(X),
.clk(clk),
.Read(Read),
.Write(Write)
);

REGFILE u1(.Rdata(Z),
.Wdata(X),
.clk(clk),
.Read(Read1),
.Write(Write1)
);


initial
$monitor($time,",X is %h, Y is %h, Z is %h Read is %d, Write is %d \n",X,Y,Z,Read,Write);

endmodule



Try the above code and let me know if you face any prolem !!!

verilog testbench generate instances access

dcreddy! your code did nt work at all. I get xxxxxxxxxxxxxxxxxx.

See the question is i want to read the contents of RAM from an instance which is different from the instance that wrote into it.

That means if i have written RAM using instance u0, i want to read the written contents using instance u1 as shown above. Since it is RAM, i should be able to do it.

Added after 2 minutes:

To make things more clearer, how would i read and write RAM in different modules of my project making sure that i have one single RAM whom i am reading or writing in different modules of my project?

note for code verilog test bench for ram

Hi Tariq,

If i understood u r question, i will repeat it once more :

you want to write in to RAM0 at the same time you want to read from RAM1 or viceversa

If this has to be happend and make generic, first thing which you need to do, you have to create a top level RAM file and instantiate two RAM modules and you have to have control logic generating write and read signals for RAM0 and RAM1 based on global read and write signals. Some how you have put priority scheme for RAM0 or RAM1 in that control logic.

If you dont want to go for that above appraoch, then apply the stimuli for read and write signals properly. This was done wrong by you in the current testbench.

lets take an example : if you want to write to RAM0 and read from RAM1, you have to have write = 1 and write1 = 0 as well as read = 0 and read1 = 0.

I hope you got what i am trying to say. If this is not what you intended, let me know


One more thing Tariq :

I have just simulated the code which i have given to you yesterday,

I have forgot and use write and read signal names instead Write and Read and i dont know how it has compiled for you without changing these names. After i have changed the naming, this is what i have got after the simulation :

add wave sim:/ram_tb/*
run
# 0,X is 00000000000000000000000000000000, Y is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, Z is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Read is 0, Write is 0
#
# 15,X is 00000000000000000000000000000000, Y is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, Z is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Read is 0, Write is 1
#
# 25,X is 00000000000000000000000000000000, Y is 00000000000000000000000000000000, Z is 00000000000000000000000000000000 Read is 1, Write is 0
#
# 35,X is ffffffffffffffffffffffffffffffff, Y is 00000000000000000000000000000000, Z is 00000000000000000000000000000000 Read is 0, Write is 0
#
# 50,X is ffffffffffffffffffffffffffffffff, Y is 00000000000000000000000000000000, Z is 00000000000000000000000000000000 Read is 0, Write is 1
#
# 60,X is ffffffffffffffffffffffffffffffff, Y is ffffffffffffffffffffffffffffffff, Z is ffffffffffffffffffffffffffffffff Read is 1, Write is 0
#
# 70,X is ffffffffffffffffffffffffffffffff, Y is ffffffffffffffffffffffffffffffff, Z is ffffffffffffffffffffffffffffffff Read is 0, Write is 0
#



Regards,
dcreddy