Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Calibre LVS and extraction

Status
Not open for further replies.
P

pokemonstation

Junior Member level 1
Junior Member level 1
Joined
Mar 4, 2009
Messages
19
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,475
calibre lvs

Hello all,

I am having trouble with Calibre LVS. My problem is that Calibre LVS does not recognize the pins I placed in the layout. For example, in an inverter my schematic has 4 ports (in, out, vdd!, gnd!) but Calibre LVS states that my layout has 0 port, despite I labeled all 4 ports in the layout. I have tried to use Create -> Pin or Create -> Label to label pins in my layout, but none of them works. Does anyone know what I should do to label pins in my layout so they are recognized by Calibre LVS?

My second problem is with Calibre extraction (PEX). I was able to extract a netlist with parasitic capacitance and resistance, but the pins/nets in the resulting netlist are not labeled as I wanted in my schematic, despite I specifically set the extraction option to use schematic nets. Does anyone know a solution to this? Do I have to have a successful and error-free LVS run in order for this to work?

Thanks in advanced!
 

calibre lvs diode

pokemonstation said:
Calibre LVS does not recognize the pins I placed in the layout.
Click to expand...
Two possibilities:
1) all the labels shorted bye mistake.
2) wrong layer selected for label....use pin or tt layer for label which tool you are using..?

pokemonstation said:
Do I have to have a successful and error-free LVS run in order for this to work?
Click to expand...
yes.

Added after 46 seconds:

any other errors your are getting from lvs?
 
calibre extraction

yes, the first problem is solved by checking whether your label layer is consistent with the metal layer wiring line.
 
calibre lvs diode between vdd gnd

hello, thanks both for your replies.

I am using Cadence Virtuoso IC 6.1.3 layout editor. I am fairly sure that I selected the right material in the LSW before I place pins/labels. For example, my VDD and ground rails are on metal 1, so I select "M1: drw" before I create pins/labels. I did try the Pin layer "M1: pin" but it didn't work. What's tt layer though?

I think this is the only LVS error I had; # of instances and device parameters all matched.
 

calibre lvs recognize pins

Actually, LVS is working now! I guess depending on the PDK (I am using IBM 65nm cmos10lpe), the layer needed might be different. Turned out that I have to Create -> Label with the "lbl" (label) layer with the matching metal/poly.

I also disabled the environment variable PEX_RUN = TRUE, which always creates a diode between VDD and ground rail (and forces me to add a diode in my schematic)

Still, with a working LVS, I still cannot get the parasitic extracted netlist to use the net names from either the schematic or the layout. Does anyone know solutions to this?
 
  • Like
Reactions: bdkjf

    B

    bdkjf

    Points: 2
    Helpful Answer Positive Rating
lvs extarction using calibre

pokemonstation said:
Actually, LVS is working now! I guess depending on the PDK (I am using IBM 65nm cmos10lpe), the layer needed might be different. Turned out that I have to Create -> Label with the "lbl" (label) layer with the matching metal/poly.

I also disabled the environment variable PEX_RUN = TRUE, which always creates a diode between VDD and ground rail (and forces me to add a diode in my schematic)

Still, with a working LVS, I still cannot get the parasitic extracted netlist to use the net names from either the schematic or the layout. Does anyone know solutions to this?
Click to expand...
Thank you for your back-info! Perhaps the following note might help?
Especially the paragraph: "In the simulation information section ..." (case sensitivity of node & model names).
 

Attachments

  • extracted_parasitic_simulation_using_calibre_1466.pdf
    93.6 KB · Views: 347

calibre lvs schematic viewer

tt layer we had used for creating labels (pins) for umc90..
 

Hi erikl,
In your pdf, you mentioned "Now, within ADE add the netlist to the model setup". I dont understand this point. Can you please elaborate on this point.
Also, do you have experience using calibreview. I got the extracted view from the layout in calibre format. But the calibre view gave the schematic with like 513 errors all are like "No default connection..." or "could not find mapping file pin...". I am using the cell map given in the cmrf8sf kit.
Thanks in advance.
 
  • Like
Reactions: syxj

    S

    syxj

    Points: 2
    Helpful Answer Positive Rating
Usman Hai said:
"Now, within ADE add the netlist to the model setup".
I dont understand this point. Can you please elaborate on this point.
Click to expand...
Hi Usman,
in the ADE window, via Setup select Model Libraries .... In this window add the full path of the extracted netlist to the standard model setup.

Usman Hai said:
Also, do you have experience using calibreview.
Click to expand...
Sorry, no. I've just used the extracted netlist(s) for postLayout simulation.

Happy New Year! erikl
 
Hi erikl,

I having problem understanding the pdf you given. Can you suggest any more details reference or guides? thank you...
 

ansonyeap said:
Can you suggest any more details reference or guides? thank you...
Click to expand...
See this thread! **broken link removed**
 
Last edited by a moderator:

hi erikl

thanks, your info was helpful for me
 

thank you for the reply. I have a glanced at the guide and there didn't talk about calibre xRC, parasitic extraction and post-layout simulation.... where can i find the information? thank again.
 

ansonyeap said:
... calibre xRC, parasitic extraction and post-layout simulation.... where can i find the information?
Click to expand...
Try here!
 

Yes, I have the sampe question mentioned here, I use the layer ll
 

you have to see in LVS deck which layer are used to represent pin. It could be tt or lvs or pin.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top