puppet.rhapsody
Newbie level 5
op amp signal conditioning
Hi, all
I am trying to design an input circuit for an ADC. ADC1173 is already selected for our design. To obtain a stable reference voltage for the chip, the circuit shown below is suggested. The reason, according to the spec. sheet, was that this op-amp circuit has low source impedance, reducing possible noise. Before I go ahead and blindly follow the suggested circuit diagram, I was trying to understand operational principle behind it, first. Unfortunately, it is not working well.
My main question would be ...
1. does the op-amp, LMC662, operate as simple buffer, even if it has bjt connected on the output node ?
2. what would be the output voltage of the op-amp, across the 100 ohm registor before the bjt ?
I don't have access to a reliable simulation program with a good library, so I can't trust ones that I tried.
I'm a junior engineer in co-op and still learning. Any intuitive advice would be really appreciated.
Sincerely,
YUI
Hi, all
I am trying to design an input circuit for an ADC. ADC1173 is already selected for our design. To obtain a stable reference voltage for the chip, the circuit shown below is suggested. The reason, according to the spec. sheet, was that this op-amp circuit has low source impedance, reducing possible noise. Before I go ahead and blindly follow the suggested circuit diagram, I was trying to understand operational principle behind it, first. Unfortunately, it is not working well.
My main question would be ...
1. does the op-amp, LMC662, operate as simple buffer, even if it has bjt connected on the output node ?
2. what would be the output voltage of the op-amp, across the 100 ohm registor before the bjt ?
I don't have access to a reliable simulation program with a good library, so I can't trust ones that I tried.
I'm a junior engineer in co-op and still learning. Any intuitive advice would be really appreciated.
Sincerely,
YUI