If you need help with ESD... ask me in this post

esd-diodesata

This is a forum item specifically targeted at on-chip ESD discussions.

If you are running into problems with ESD or are uncertain about the selected approach you can post it here. I ('ESDsolutions') and other EDAboard members will help you as much as possible, point you to the right information online or provide opinion, experience.

ES

esd site:www.edaboard.com

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Great topic! I have two questions that could use some insight:

1.) I understand that there are two different "flavors" of ESD protection: one that protects from static during the manufacturing process, and one that protects from static during use and handling. Is this correct? Can you expand upon the differences and provide some advice about which is more important in a research setting? What specifically is done in the pads differently for the two cases.

2.) If ESD protection from manufacturing static is critically important, how can you protect against it for pads where leakage is critical? i.e. if I need to measure pA level currents from a pad, i cannot tolerate the junction leakage of an ESD diode. what to do then?

Thanks!

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miznick said:

Great topic! I have two questions that could use some insight:

1.) I understand that there are two different "flavors" of ESD protection: one that protects from static during the manufacturing process, and one that protects from static during use and handling. Is this correct? Can you expand upon the differences and provide some advice about which is more important in a research setting? What specifically is done in the pads differently for the two cases.

2.) If ESD protection from manufacturing static is critically important, how can you protect against it for pads where leakage is critical? i.e. if I need to measure pA level currents from a pad, i cannot tolerate the junction leakage of an ESD diode. what to do then?

Thanks!

Click to expand...

There are different threat signatures (charge stored, limiting impedances, etc.) for different environments (machine, handling) but the right answer for the ESD designer is "all of the above". Some end uses demand higher ruggedness than others - things attached to cables that leave the box, for example, see ESD level as a competitive differentiator and go for 10kV+, while manufacturing is happy enough with 2kV.

As to leakage, sometimes you have to negotiate your way out of an untenable performance / reliability "box". Not everything can be solved by hardware.

Dear miznick. Thank you for the interesting question.

dick_freebird is right: The required ESD protection actually depends on the end customer as well as on the manufacturing capabilities.

The end customer may want to increase the specification because of fears of ESD during actual use. Think of USB or HDMI ports used in a home setting. I don't know many kids wearing wrist straps when connecting their blu-ray player to daddy's new plasma screen. Therefore system makers include system level ESD protection and request stringent ESD specs for the ASIC's with direct connection outside the system.

Beware: sometimes it is the competition that sets the requirement. E.g. I know of an IC that allowed the end systems to reach 8kV IEC protection (well above the 6kV target) that was still denied by the OEM because the competing ASIC reached 10kV IEC.

You need protection on the pads to ensure high enough yield during manufacturing. All kinds of human/machine handling (e.g. bonding) can result in destruction of the circuits on the chip due to ESD. Of course, foundries and assembly houses now use strict ESD control methods to reduce the threat. This means that you always need some protection or be OK with a reduced yield.

However, I tend to believe that Miznick is mainly interested in using the test-chip for research and has no plans (yet) to sell it to an end-customer. Then the question is about the right level to ensure that there are enough good dies reaching the research lab. It would be a real pitty to wait 2 months, pay 10.000 $ finally to get a bunch of dead circuits.

Some companies (lead by TI, Infineon) are trying to convince the entiry industry to jointly reduce the required level used today (typical 2kV HBM - 200V MM) to 500V HBM based on a 'huge amount of data' of chips with 500V HBM level that still survived the manufacturing and assembly process: see **broken link removed**

To be honest, the 'huge amount of data' shown does not convince me. They might be right but do not have the data yet to proof it.

I think that most in the industry acknowledge that the 2kV HBM level used for many decades might be reduced for products in ESD controlled environments. The problem is that it is hard to quantify the minimum required protection level. People have tried measuring the voltages on various places in the manufacturing environments (e.g. 100V) and coupled this to HBM/MM levels required. For sure this is not the right approach!

Conclusion: When you are sure about the ESD control used (up until you are using the circuits in the lab) you could follow the proposal from TI/IFX to design for 500V HBM protection.

With this HBM level and the right protection approach and optimized clamp/diode layouts you should be able to reach below 10pA leakage currents (based on 130nm TSMC achievement) for the IO's. I hope this helps![/url]

How about adding resistors, i know a couple of designs that can be quit intolerable to ESD resistance (even few Ohms)

Can the IC survive if it depends solely on the Diodes?

ESD solutions:
I believe that most of the "RF or highspeed product suffer due to 2kV spec. For those product it is really hard to make ESD protection since it requires very low capacitance on the node. And often the ESD of 2kV is waived for those I/Os.
Also most of similar products are not in contact with "world" and the board they are on is ESD protected. What those companies ask for makes sense.

Hi Teddy

Thanks for replying and clarifying. You are right that it is more difficult to protect high speed pins (Gbps for USB 3.0, SATA, PCIexpress, HDMI) and RF IO's.
And you are right that it makes sense to reduce the specification.

However I have some concerns:
Many will agree that it is not impossible to protect those pins even to 2kV and higher. I have seen 3.4 Gbps TMDS HDMI pins that are protected above 8kV, 10 Gbps communication chips that reach 4kV HBM, 5GHz LNA's with 5kV and more. With the right solutions and expertise it remains possible, even in advanced nodes like 65nm, 40nm.

But don't take me wrong: I believe there is room to reduce the specification but it is hard to quantify this new level: We'll need other data points, different from the currently used.

Most importantly: Reducing the specification should not be related to the fact that it is technically impossible in advanced nodes to reach 2KV. But it should be related to the fact that there is margin to reduce the specification without additional returns.

Added after 39 minutes:

Dear safwatonline

Indeed: some IO types cannot tolerate resistance. This means that you cannot rely on the standard/generic purpose IO solution and will need a custom/special ESD clamp approach.

Unless you have a very big power domain (lots of Vdd-Vss capacitance), the dual diode at the IO's is not sufficient. To close the loop for the ESD current injected at the IO versus ground you need a power clamp circuit between Vdd and Vss lines. There are quite a lot of different approaches for power protection, each with their own benefits.

But I think you meant it differently. The feasibility of the "Dual diode" approach depends on many factors:
- What is the voltage drop accross the power clamp at triggering and at clamping. The lower the voltage drop the easier it gets
- What is the maximum tolerated voltage at the IO under ESD conditions. This depends on the technology and on the IO topology used. The lower the voltage the more difficult it gets. E.g. a thin oxide in 130nm directly connected to pad will fail at ~5V. That is close to the edge of the dual diode approach

Conclusion: yes, dual diode can be sufficient at the IO unless the IO circuitry is very sensitive (low failure voltage).

Hi!

I am trying to set up the correct test bench for ESD HBM in an on-chip PAD.

My approach is to create the correct ESD HBM and then to build a rail-to-rail ESD protection circuit attached to the PAD.

I want to verify my thinking, so I would appreciate any suggestions or guidance on doing the above steps.

Thanks,

D.

ESDSolutions,
I want to know the basic principle that the second stage ESD protection structure could protect the input transitor's gate. Thanks very much!
For example,A large GGNMOS followed by a resistor and a small GGNMOS.
which transistor turn on before the other one?

Thanks very much!

Hi Mengcy

When you are using a secondary protection concept you typically have 2 DIFFERENT stages. One primary current path is created for the majority of the ESD current. This typically consists of a diode + bus resistance + power clamp for an IO to VSS stress case. For IO pads far away from the power pads (e.g. large bus resistance) the total voltage drop between IO and VSS can become very high causing destruction of the IO circuitry.

As an example, take a 90nm thin oxide gate connected to IO. It will fail at about 5V (short pulse). It could happen that the power clamp, diode up and bus resistance together build up 10V at 3 ampere of ESD current.

Therefore you add a local protection clamp that clamps the voltage to a lower value. A typical local clamp will be a ggNMOS device but for advanced CMOS (90nm and beyond) the effectiveness is strongly reduced as its trigger voltage is close to the transient oxide breakdown voltage. The idea is that the local clamp limits the voltage over the oxide below 5V. The difference (10V through primary protection path) is the voltage drop over the isolation resistance between the primary ESD and the secondary ESD device. This means that you can calculate the resistor value based on the voltage difference and current capability of the secondary protection clamp.

Mind that the large voltage drop can occur at full ESD current (example above) but can also occur before triggering of the primary current path. Both situations should be looked at!

ES

Hi all,

I am building a HBM ESD test bench and I came up to the following question:

When I connect the ESD protection circuit and the theoretical input to the main circuit (ie an n-MOS),
what I put as Vcc and Vee voltage of the ESD?

My original idea is to leave it floating. But then, floating means arbitrary voltage in the power lines.

My second thought is to put both VCC and VEE inputs to the same node which eventually is connected to the substrate.

The second approach shows a well operating ESD protection scheme. But is it the correct one, meaning, is it the one corresponding in the real situation?

Thanks,

D.

Hello all,
I have question regarding protecting the Drain of an analog switch (transmission gate) that is connected to an IO pad. (0.18um TSMC CMOS mixed-signal process).
The standard IO ESD cell from TSMC has the 2 diodes to vdd and vss. I'm wondering if it is necessary to build/layout the analog switch transitors following TSMC IO device guideline (since these devices are directly connected to the outside world).
Following IO devices rules means extending the drain and 'non-silicided' the extended portion (basically adding ballasting resistor on each transistor finger). This greatly increase the area of the switch, which already quite big (Wtotal=6000um).

I've heard from difference sources that in such situations, you really don't need to use special ESD layout protection techniques for the analog swithc devices. Is this true?

sincerely,
RC

Hi RC,

Thank you for your question.

It is true that in some cases the analog switch will be safe even without dedicated protection. However in my opinion it depends on the stress case, gate and bulk bias of the switch and also on the circuitry connected to bulk/gate. Moreover, it could be OK for 2KV HBM for instance but not for higher requirements. If it is a Multi Project Wafer you could take the risk. For a final product tape I would advice to use another option!

You mention two options for ESD protection: either ‘dual diode’ or ‘self protective’ switch (TSMC IO device guideline). In case of the dual diode the effectiveness will strongly depend on the power clamp. If you are using a ggNMOS based power clamp then I wish you luck!

Of course there are more options like the use of local clamps. For 180nm TSMC our company Sofics has already silicon proven solutions available. Let me know if you would like a discussion on acquiring such solutions.

Regards

ES

Hi ES,
Thank you very much for your reply.
If you can allow me to poke your brain further, here's the scenario I'm planning to use:

The switch transistor widths are 1500um for N and 500um for P (L=0.4u), and thier gates are driven to Vdd and Vss through inverters (and therefore no directly connetion of the gates to the supply lines); bulks are tied to Vdd and Vss for N and P transistors. The drain of the switch directly connects to IO pad, with an ESD structure (std TSMC IO, with diodes to Vdd and Vss). Vdd-Vss clamps are also placed in the IO ring near these pads - the clamps are RC 'transient' based clamps (RC connectes to an inverter driving an NMOS clamp between Vdd & Vss).

I don't want, for the switch transistors, to follow the TSMC ESD guide line of putting an extra 1.95um distance from the drain side contacts to the gates (and non-silicide the drains) because of area and parasitic reasons. (need to pass signals at 500MHz). My worry is, ESD current will go through the dain to substarte unevenly and find only a few 'fingers' to go through, and fry the switch.
I'm hoping that with a transistor size that large, even a portion of the fingers gets turned on (the diffusion dioides); it'll still be OK....

2kV HBM is our aim.


thank you much for any advise
Raymond

Hello ESD,

I have a lot of questions

I see some rather high ESD protection levels in analog switches i.e., 10kV or more. Is there anything special involved in reaching these levels?

I have begun to use a process that has silicide. I read about using substrate pumps to turn on the parasitic npn sooner and get all fingers turned on. Is this because ballasting is not possible with silicide? Does anyone substrate pump the output mosfets directly rather than use ESD devices?

Hi Raymond

If your are not following the foundry ESD rules for the NMOS/PMOS switch devices then you should not count on these devices for shunting ESD current at all.
Actually without some silicide blocking you better completely prevent 'snapback' in the transistor - snapback in one finger will lead to destruction / shorted finger before additional fingers 'come to rescue'.

All of the ESD current should flow through the dedicated ESD devices. In your case this means the ESD diodes and the power clamp. You may use techniques to increase the ESD design window of the switch devices but this will complicate the pre-driver design. Another option is to use local clamps with low enough trigger voltage.

ES

Added after 6 minutes:

Hi Snafflekid

Some vendors are indeed claiming 10kV HBM levels for their analog switch products. For sure they are using special ESD protection elements placed at the IO. For these high ESD currents most will use some kind of SCR based approach because the traditional devices and techniques would yield large parasitic capacitance.

Substrate pump: I believe TI has used substrate pumped silicided output drivers. They have patented a number of techniques.
Ballasting is certainly possible even if you do not have silicide blocking. A special MOS layout technique called Back-end-ballasting for instance is patented by Sofics. It yields lower parasitic capacitance, resistivity and smaller area for the same ESD protection as compared to silicide blocked approaches.

ES - EsdSolutions

ESDSolutions,
VDD-VSS clamp is being developed, The clamp is NMOS with RC triggering( RC connect to an inverter driving an NMOS clamp between VDD&VSS), as shown in figure. The process is 0.13um TSMC process. There are two structure NMOS clamp. One is non-silicided NMOS with 1.95um distance from the drain side contacts to the gate, following TSMC ESD design guide. The size is 45um/0.4um *12. The other is silicdied NMOS as normal NMOS. The size is 25um/0.4um *60. Which structure is better?
Thanks very much.

skymusic
i think both options are fine since TSMC offored to the customer, they should have tested the roubustness of both schemes.
but i couldnt figure out why they prefer to use an inverter to help triggering. it could be triggered on very fast already even without the inverter .
and my another concern is how much voltage should be coupled on to the gate of the power clamp deivce. some paper mentioned that the gate voltage should be kept at an optimal vaule but not completely follow the voltage at the power supply at ESD event. if that is ture, the RC costant should be set very large and no inverter should be added at all.
so i'm confused how to set the optimal R and C vaules, with or w/o the inverter?

thanks