VCO phase noise reduction techniques

vco phase noise

Hello,


I have a differencetial four stages fully CMOS VCO (3.5Ghz-4.5Ghz). The phase noise measured is -63 dbc/hz @ 1 Mhz offset at 4 Ghz.

Is there some techniques to reduce the VCO Phase noise ?
How to find the optimal transistor sizing for obtaining the less possible phase noise.

Thanks in advance.

lc vco phase noise 2009

Hi,
As the power increased, the phase noise decreased
best regards,
Rania

reduce vco phase noise

do some noise calculations by hand to see the noise contribution being injected into the tank. Should look at flicker and thermal noise mainly. If you are using cadence then the noise summary will list your individual device's noise contribution. then just minimize noise accordingly using equations found in most texts/lecture notes. An example would be say for flicker noise from your tail current mirror (if you have one). Usually this flicker noise is huge and gets up converted into the vco, one way to reduce it is to increase (W*L), another way is to reduce current, but current will if designed properly reduce your swing thus decrease phase noise even more so best is to increase the transistor size of the tail for flicker noise. Alternatively you can add a resonator which shorts all low frequency current noise generated by the tail so theres no upconversion. Transistor sizings will depend on which type of noise dominates in your circuit, increase gm to minimize voltage noise, minimize gm to reduce current noise. Use fingers to reduce gate resistance hence thermal noise. When you've optimized all the elements, the mosfets that make your -ve resistance should dominate noise contribution, then its a trade off between startup/reliability and noise injected into the tank. As rania said, increasing current will increase swing and reduce phase noise.

phase noise reduction

Ring VCO usually has bad phase noise , you can see the noise contribution for each device by cadence, and to decrease device flicker noise increase its area while to decrease its thermal noise increase the power , beware that increasing the area will mean also increasing the power for the same frequency due to the added parasitic capacitance specially at this frequency you mentioned. beware also that you will need to increase the power largely to gain few dB`s in phase noise . if you need much higher phase noise then it is the time to go for LC VCO !
good luck!

noise reduction techniques

the simulation results of Cadence follow the analytical methods from Ali Hajimiri.
"A general theory of phase noise in electrical oscillators"
Reading his paper,there are many methods to improve the phase noise of the VCO.
First,you may increase the output swing,which relates to the qmax.
Second,you may reduce the rise time and fall time by increasing the tail current.
This cause a smaller intensive sensitive function.
Third,you should increase the symmetry of the output waveform.this cause a smaller f(1/3).
Also,I found that increase number of stages would help.
Good luck