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AMBA -AHB, HREADYIN at slave ???

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uditkumar1983

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amba ahb slave

Hi Friends,
In AMBA-AHB Slaves on the bus require HREADY as both an input and an output signal.
and as I know significance of HREADY (O/p of slave) will tell when it is ready to accept new transfer.
and HREADY (i/p of slave) will tell when transfer is complete....
Please anybody can discuss me in more detail about HREADY as Input for slave ...
In Which condition we have to used it, whats r advantage of it ??

Thanks in Advance ..

Regards
 

hready_out

Hi Friends,
I am waiting your suggestions ....Please give me your suggestions.

Regards
 

hready signal in ahb bus

AMBA AHB slave doesn't have input hready signal, it just output it , please check the amba spec at P79
 
ahb hreadyin hreadyout

I've seen many AHB implementations with HREADY in signal.

This is used to know when the previous transaction is over.
 
difference hready_in and hready_out

Hi Friends,
Phoenixfeng you r wrong , AMBA AHB is having HREADY on slave both as input as well as output .
AMBA AHB slave have input hready signal to know when the previous transaction is over. For clarification see AMBA document at page 2-4.
for ur reference i m wriiting this here ....and this is used in my third Party IP ...........
[HREADY:Transfer done
Slave When HIGH the HREADY signal indicates that a
transfer has finished on the bus. This signal may be
driven LOW to extend a transfer.
Note: Slaves on the bus require HREADY as both
an input and an output signal.]

So if any one of you having more info about it then Please discuss with me ...

Regards
 

hreadyin ahb

yes,AMAM using HREADY slave input to let slave determine whether the mater was get ready to receive the data required by master.
perhaps after maser send the read data fetch,there is a interrupt that lead to the mater cannot perform the operating immediately
 
arm ahb slave ready

uditkumar1983 said:
Hi Friends,
Phoenixfeng you r wrong , AMBA AHB is having HREADY on slave both as input as well as output .
AMBA AHB slave have input hready signal to know when the previous transaction is over. For clarification see AMBA document at page 2-4.
for ur reference i m wriiting this here ....and this is used in my third Party IP ...........
[HREADY:Transfer done
Slave When HIGH the HREADY signal indicates that a
transfer has finished on the bus. This signal may be
driven LOW to extend a transfer.
Note: Slaves on the bus require HREADY as both
an input and an output signal.]

So if any one of you having more info about it then Please discuss with me ...

Regards
Click to expand...
He isn't wrong.
its not mandatory.

Regards
 
hreadyin hready ahb

Hi rsrinivas,
Yes Its not mandatory, but if required we can used it.but Phoenixfeng was telling AMBA AHB slave doesn't have input hready signal, it just output it .

Regards
 

ahblite slave to avalone slave.

Hi, uditkumar1983

slave outputs HREADY signal , not only the masters checke HREADY, but also the slave itself checks HREADY signal that it outputs. I think that's the mean of "both an input and an output signal" .
See page 3-45, can you find HREADY input signal?
FYI
 
+amba +ahb vs ahblite

HI Phoenixfeng,
I am working on such an IP which having HREADY signal as both input and as well as output and both signal are different, and if slave wants to check itself than no need to put as input port outside of slave ,slave can be used it internally ........
So this signal can be used but not mandatory .........

So if anyone is using this type , please share ur knowlege ...

Regards
 

ahb bus ready slave ready

Please refer this link
 

hready to slave

I am working on the AHB2.0, does anyone know if the ready input and output on the slave side is separated or not? or just behave as in/out put for one
 

diffrence amba versions

I have never seen an AHB slave which does not have both HREADY input and HREADY output.

Quoting from:
**broken link removed**

A key point of slave design that is not made clear by the AHB specification is that slaves will have both HREADYin and HREADYout signals. HREADYout indicates when the slave needs the master to wait before the read or write access can be completed. HREADYin comes from a mux which selects the HREADY output of the currently accessed slave. This lets the slave see the end of data phase of the transfer being done by the previously selected slave, which will mean the start of this slaves data phase.

In summary - HREADY output lets you extend the transfer (add wait states)
HREADYin lets you see when other slaves have extended the transfer. The only time you can miss out this signal is if you are the only slave in the system, or no other slave can take HREADY low.

ARM website FAQs make same point.
 
hready_in

Hi All,

Please reffer forllowing attachment for more clearification.

An AHB slave must have the HREADY signal as both an input and an output.

HREADY_OUT is required as an output from a slave so that the slave can extend the data phase of a transfer.

HREADY_IN is also required as an input so that the slave can determine when the previously selected slave has completed its final transfer and the first data phase transfer for this slave is about to commence.

Each AHB Slave should have an HREADY output signal (conventionally named HREADYOUT) which is connected to the Slave-to-Master Multiplexer. The output of this multiplexer is the global HREADY signal which is routed to all masters on the AHB and is also fed back to all slaves as the HREADY input.(See attachment)

I have made AHBLite to Avalone bridge for that i must have to use both HREADY_IN and HREADY_OUT because i connected more then one avalone slave, if only one slave I think no need ot HreadyIn. AHBLite connected with CortexM1 Master.

--
Shitansh
 
amba ahb slave faq

Perfect! after studying knowlege donated by Shtiansh,i understand the use of hreadyin !
thanks!
yurenjie
 

Can anyone clarify what is the expected behavior of the ERROR response when coupled with the hreadyin signal?

Can first cycle of ERROR response (Cycle0 with hresp = 1 and hreadyout = 0) be provided when hreadyin = 0? What about second cycle? If hreadyin = 0 during second cycle of ERROR response, should ERROR response Cycle1 with hresp = 1 and hreadyout = 1 be extended till hreadyin = 1 ?

I understand that data can't be delivered back to the AHB master if hreadyin is not high. In many systems, I think the hreadyout is looped back to hreadyin. Is there a way to avoid the combinational loop which seems inevitable if ERROR response can only be provided when hreadyin = 1?

Thanks in advance for your help!
 

jakmal said:
Can anyone clarify what is the expected behavior of the ERROR response when coupled with the hreadyin signal?

Can first cycle of ERROR response (Cycle0 with hresp = 1 and hreadyout = 0) be provided when hreadyin = 0? What about second cycle? If hreadyin = 0 during second cycle of ERROR response, should ERROR response Cycle1 with hresp = 1 and hreadyout = 1 be extended till hreadyin = 1 ?

I understand that data can't be delivered back to the AHB master if hreadyin is not high. In many systems, I think the hreadyout is looped back to hreadyin. Is there a way to avoid the combinational loop which seems inevitable if ERROR response can only be provided when hreadyin = 1?

Thanks in advance for your help!
Click to expand...

You can't give the first part of the ERROR response when some other slave is still active.

When HREADYIN is low, it means some other slave is in the data phase (and is extending the data phase). The master is not looking at your HRESP and HREADYout. The two cycle response starts from when the cycle when you see HREADYin=1, indicating that you are now in the data phase. The reason that ERROR is a two cycle response is to give the master the chance to change the address & control signals for the access after the one that is causing the error. The slave doesn't need to monitor HREADYin once it is in the data phase already. It's the same case as any other transaction where you add a wait state.

In your slave design, you look at the address and control signals in the address phase of the transfer. When you see HREADYin is high, you know that the transfer has gone into the data phase. At this point, you have control of the bus until you signal HREADYout high to complete the transfer. You don't have to look at HREADYin now.
 

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