About the implement bypass function in DFT?

set_test_point_element

Hi,
I met a question in my design of DFT for a SOC chip. In this SOC, there are PLL and many memory modules. I want to bypass the memory when testing, so I change the RTL code to add a bypass function to them, but I find this method does not work.
In RTL code, I added a mux which is controlled by the test_en signal of the chip to every memory, and than in the DFT compiler, I add the definition as follow:

set_dft_signal -view existing_dft -type ScanClock -timing {4 5} -port clk
set_dft_signal -view existing_dft -type Reset -active_state 0 -port reset

set_dft_signal -view spec -type ScanEnable -active_state 1 -hookup_pin [get_pins u1/C] -port test_en

set_dft_signal -view existing_dft -type Constant -active_state 1 -port TEST_MODE

and I added a TEST_MODE signal to it. The coverage_estimate before adding the bypass function is 84.32% and the violation is all about the memory; The coverage_estimate after adding the bypass function is 89.02%(but all the violations are still there...). I think is the bypass function does not work when testing? If it works, the coverage_estimate will be much higher I think.
My question are:

1, how to implement the bypass function in DFT, changing the RTL code or any other method? which signal should I used to controled it, test_en or TEST_MODE...?
2, how to make the DFT compiler know the bypass function added by changing the RTL code when do the DFT compile?

And other question, I found this warning in the DFT reports：
Warning: Port 'reset' cannot be used as a scan port. It has been previously inferred as an asynchronous signal. (TEST-337)
This reset port is used in the RTL code, and when DFT, it is reused as the RESET signal. I found this warning comes out when define a new port for RESET or reuse the port in DFT compiler. Does it do harm to our design, please?

Thank you.
Best regard!

what is dft trough port no

About the violations I met.
The violations in DFT DRC are all about the RAM/ROM.

top_uxpord_uxlog2_uxrom (Cell top_uxpord_uxlog2_uxrom (logrom_10x10) is unknown (black box) because functionality for output pin Q[9] is bad or incomplete.)
(Total number of this violation is 11)


top_u/tQ2Item_u/rdata_b[9] (Three-state net top_u/tQ2Item_u/rdata_b[9] is not properly driven.)
(Total number of this violation is 120)


These violation come out both in before adding the bypass and after adding the bypass, and the numbers are the same.
I make a change the DFT setting, and the coverage_estimate is imcreaced to 95.6%, but these violations are still the same before and after adding the bypass.
How to solve these problem? Can the bypass function do that? And does the coverage_estimate do nothing matter to these violations?

Thank you!
Best regards!

dft memory bypass

Hello Gaom,

Instead of modifying the RTL let DFT tool fix this by inserting test points for memories.

How to insert testpoints go through my comments in the following page

or



For PLLs,
Just go through the following page
**broken link removed**

Hope this will help.

Sunil Budumuru
asic-dft.com

set_scan_element

Thank you for your reply, sunilbudumuru.
I will try it.

Best regards!

Added after 2 hours 20 minutes:

Hi, sunilbudumuru
I insert the test points to design as follows(take two as an example)

####Insert test points and bypass the memory

set_testability_configuration -type observe -clock_signal [get_ports [list clk_pad]]
set_testability_configuration -type control -clock_signal [get_ports [list clk_pad]]

####FOR INPUTS
set_test_point_element -type observe [get_object_name [get_pins [list top_u/Code_u/dp/AA* top_u/Code_u/dp/AB* top_u/Code_u/dp/DB* top_u/Code_u/dp/DA*]]] -clock_signal clk_pad -power_saving enable

set_test_point_element -type observe [get_object_name [get_pins [list top_u/Place_u/sp/A* top_u/Place_u/sp/D*]]] -clock_signal clk_pad -power_saving enable

####FOR OUTPUTS
set_test_point_element -type control_01 [get_object_name [get_pins [list top_u/Code_u/dp/QA* top_u/Code_u/dp/QB*]]] -clock_signal clk_pad -control_signal TEST_MODE

set_test_point_element -type control_01 [get_object_name [get_pins [list top_u/Place_u/sp/Q*]]] -clock_signal clk_pad -control_signal TEST_MODE

the reports as follows


Uncollapsed Stuck Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 30451
Possibly detected PT 5
Undetectable UD 1446
ATPG untestable AU 2234
Not detected ND 7
-----------------------------------------------
total faults 34143
test coverage 93.14%
-----------------------------------------------


************ Test Point Plan Report ************
Total number of test points : 352
Number of Autofix test points: 0
Number of User test points : 352
Number of Wrapper test points: 0
Number of test modes : 1
Number of test point enables : 120
Number of data sources : 20
Number of data sinks : 32
Clock name : clk_pad
Power saving logic : enable
**************************************************

The coverage without these test points is about 87%, the reports as follow:
Uncollapsed Stuck Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 20732
Possibly detected PT 47
Undetectable UD 4518
ATPG untestable AU 2773
Not detected ND 96
-----------------------------------------------
total faults 28166
test coverage 87.77%
-----------------------------------------------

and the report of adding the bypass function in RTL code are as follows:

Uncollapsed Stuck Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 27224
Possibly detected PT 0
Undetectable UD 3058
ATPG untestable AU 861
Not detected ND 10
-----------------------------------------------
total faults 31153
test coverage 96.90%
-----------------------------------------------

************ Test Point Plan Report ************
Total number of test points : 0
Number of Autofix test points: 0
Number of Wrapper test points: 0
Number of test modes : 0
Number of test point enables : 0
Number of data sources : 0
Number of data sinks : 0
**************************************************

I think adding the test_points by the set_test_point_element command will add so many logic or DFF modules to the design, is that right? And in this design there are 44 DFFs can not be tested no matter in any bypass method(44 cells are non-scan shift-register cells). How can I locate them and fixed them? How to increase the coverage in this condition。

Thank you!
Best regards!

www.asic-dft.com

If they are non scan flops, your test coverage may reduce as u are excluding these flops. However u can mention either
"set_scan_configuration -exclude_elements [get_cells ....] or "set_scan_element" based on the requirement.

In the above case you need not to by pass the elements, tool will take care i guess.

Do one thing, u mention above stwitches to the required elements to be excluded from scan chain. and insert_dft.

Yes, it will have little area over head. If some memory elements are excluded, it will have effect on test coverage.

-sunilb

dft test point plan report

Hi, sunilbudumuru
I don't understand the thing you told；

Do one thing, u mention above stwitches to the required elements to be excluded from scan chain. and insert_dft.

What is the meaning of "stwitches"? Is it switches?
Do you mean I should exclude the 44 DFFs I mentioned above from the scan chain?
But I can not locate where are they？ Can DC report the Undetectable DFF or non-scan shift-register cells by any command?

Thank you!
Best regards!

uncollapsed stuck fault summary report

I said If you want to exclude the specific registers from stritching u can use the switches (variables like set_scan_configuration -exclude_elements [get_cells ....] or "set_scan_element").Then tool will ignore these registers from stritching (during insert_dft)

You can report the non scan cells or u can see the non scan registers in the dft_drc reports

Re: dft memory bypass

hi Sunil Budumuru,
i am not able to open this link..
what i have to do to access it..

For PLLs,
Just go through the following page
**broken link removed**

Hi,

Can anyone give me the command that will just give the list of non scanable registers in design after inert_dft?

I searched in user guide but couldn't find.

Regards,
Vid31