tariq786
Advanced Member level 2
verilog measuring period
Dear Folks,
I synthesized AES (Advanced Encryption Standard) verilog core that i downloaded from www.opencores.org. For synthesis i used Synopsys Design compiler and tsmc180nm library. During synthesis, i specified the clock period constraint to be 5ns or (200 MHZ) and Design Compiler showed no violation of the period constraint during synthesis.
After synthesis, i did post synthesis verilog simulation. Here i started getting setup and hold time violations with 5ns clock period and had to increase clock period by a factor of 40 i.e. 200ns (5 MHZ) to get valid results.
I am confused either post synthesis frequency of 5 MHZ is the true frequency of the design or pre synthesis frequency of 200 MHZ is the true frequency of the design.
I also did PrimeTime static timing analysis of the design after synthesis and it also had no problem with the period constraint of 5ns.
I must mention that post synthesis verilog simulation of the design is dynamic one that is you have to give test_vectors in a test bench to get outputs while primetime and design compiler using static timing methods without any test vectors to report the maximum frequency.
Thanks for your help.
Dear Folks,
I synthesized AES (Advanced Encryption Standard) verilog core that i downloaded from www.opencores.org. For synthesis i used Synopsys Design compiler and tsmc180nm library. During synthesis, i specified the clock period constraint to be 5ns or (200 MHZ) and Design Compiler showed no violation of the period constraint during synthesis.
After synthesis, i did post synthesis verilog simulation. Here i started getting setup and hold time violations with 5ns clock period and had to increase clock period by a factor of 40 i.e. 200ns (5 MHZ) to get valid results.
I am confused either post synthesis frequency of 5 MHZ is the true frequency of the design or pre synthesis frequency of 200 MHZ is the true frequency of the design.
I also did PrimeTime static timing analysis of the design after synthesis and it also had no problem with the period constraint of 5ns.
I must mention that post synthesis verilog simulation of the design is dynamic one that is you have to give test_vectors in a test bench to get outputs while primetime and design compiler using static timing methods without any test vectors to report the maximum frequency.
Thanks for your help.