How to view the layout contents of the instances?

bfmoat

I can see the transistors layouts when designing the layout of a transistor level design. But at the top-level layout design, when i come to connect the designed layouts, i only see empty boxes.

Please, can you tell me how can i view the layout contents of the instances instead of empty boxes?
I tried pressing SHIFT-F but it did not work.

m1_cad

try All visible (AV) option in LSW

al_rdl layer

load techfile again from LSW and then use AV option. This should work.

m1_cad/dummy_block cadence

sorry to say that there was no change!

Do you have any other ideas?

Added after 52 minutes:

in the icfb window it says:

*Error* eval: undefined function - controls
*Error* load: error while loading file - "/usr/local/tools/work_umc130/umc13mmrf.tf"


what can i do? please help

chnglyr

Its not taking techfile as i already suggested( .tf).. you need to load it.. if you are still facing problem, feel free to contat one of you CAD team member for respective path...

You can load the techfile from LSW
Edit->load and then giving path if required..

po_lvs

thanks a lot for your help deepak, i do appreciate it.
I entered the path correctly, but i do not know why cadence doesn't understand the functions in the techfile.
I will paste the techfile, in case it helps.



; Technology File umc13mmrf

;********************************
; CONTROLS
;********************************
controls(
techParams(
;( parameter value )
;( ---------- ----- )
( maskGrid 0.01 )
( cadGrid 0.01 )
( drcGrid 0.01 )
( mfgGrid 0.01 )
( scale 1.0 )
) ;techParams

) ;controls


;********************************
; LAYER DEFINITION
;********************************
layerDefinitions(

techPurposes(
;( PurposeName Purpose# Abbreviation )
;( ----------- -------- ------------ )
;User-Defined Purposes:
( LL_PWELL 1 LL_PWELL )
( HV_PWELL 2 HV_PWELL )
( LL_NWELL 3 LL_NWELL )
( VTP 4 VTP )
( VTN 5 VTN )
( HVNW 6 HVNW )
( VTPH 7 VTPH )
( VTNH 8 VTNH )
( VTPL 9 VTPL )
( VTNL 10 VTNL )
( HVNLDD 11 HVNLDD )
( HVPLDD 12 HVPLDD )
( CELLSD 13 CELLSD )
( SAS 14 SAS )
( CELL_VTN 15 CELL_VTN )
( CELL_VTP 16 CELL_VTP )
( CELLISO 17 CELLISO )
( CELLC 18 CELLC )
( ONO 19 ONO )
( CELLG 22 CELLG )
( MVC_MARK 25 MVC_MARK )
( BFMOAT 26 BFMOAT )
( IND 27 IND )
( L1_MCAP 28 L1_MCAP )
( L1_ROUT 29 L1_ROUT )
( Dummy_Block 30 Dummy_Block )
( Slot_Block 31 Slot_Block )
( Dummy 32 Dummy )
( Slot 33 Slot )
( OPC 34 OPC )
( Block 35 Block )
( BAR 36 BAR )
( OPC_Block 37 OPC_Block )
( PWR 38 PWR )
( LOGO 39 LOGO )
( MACROMK 40 MACROMK )
( FRAMMK 41 FRAMMK )
( BOUNDMK 42 BOUNDMK )
( Resistor_Mark 43 Resistor_Mark )
( Metal_Port 44 Metal_Port )
( TEXT 45 TEXT )
( NT_MARK 46 NT_MARK )
( FGCMARK 47 FGCMARK )
( MRSYMBOL 48 MRSYMBOL )
( CSYMBOL 49 CSYMBOL )
( BJTSYMBOL 50 BJTSYMBOL )
( DSYMBOL 51 DSYMBOL )
( DIOBLK 52 DIOBLK )
( LSYMBOL 53 LSYMBOL )
( MMSYMBOL 54 MMSYMBOL )
( RFSYMBOL 55 RFSYMBOL )
( RFMOS_S 56 RFMOS_S )
( F_MOS 57 F_MOS )
( SIZE1 58 SIZE1 )
( SIZE2 59 SIZE2 )
( SIZE3 60 SIZE3 )
( SIZE4 61 SIZE4 )
( SIZE5 62 SIZE5 )
( SIZE6 63 SIZE6 )
( SIZE7 64 SIZE7 )
( SIZE8 65 SIZE8 )
( SIZE9 66 SIZE9 )
( SIZE10 67 SIZE10 )
( SIZE11 68 SIZE11 )
( SIZE12 69 SIZE12 )
( SIZE13 70 SIZE13 )
( SIZE14 71 SIZE14 )
( SIZE15 72 SIZE15 )
( SIZE16 73 SIZE16 )
( HVMARK 74 HVMARK )
( MVMARK 75 MVMARK )
( PO_LVS 76 PO_LVS )
( SP_1 77 SP_1 )
( SPLL 78 SPLL )
( SPLL1 79 SPLL1 )
( RF2P_1 80 RF2P_1 )
( RF2PLL 81 RF2PLL )
( DP1 82 DP1 )
( DP2 83 DP2 )
( ROM_ID 84 ROM_ID )
( CELLMARK 85 CELLMARK )
( TCAM1 86 TCAM1 )
( TCAM2 87 TCAM2 )
( HD2P 88 HD2P )
( RF2P 89 RF2P )
( RFPADMK 90 RFPADMK )
( BOACMK 92 BOACMK )
( CUST_2 93 CUST_2 )
( FILLERBK 94 FILLERBK )
( IND_UPS 95 IND_UPS )
( WELLBODY 96 WELLBODY )
( ONOCAP 98 ONOCAP )
( MCAP 99 MCAP )
( DIFFBK 100 DIFFBK )
( OPC_444_Block 101 OPC_444_Block )
( OPC_444LL_Block 102 OPC_444LL_Block )
( OPC_228_Block 103 OPC_228_Block )
( OPC_228LL_Block 104 OPC_228LL_Block )
( OPC_466_Block 105 OPC_466_Block )
( OPC_466LL_Block 106 OPC_466LL_Block )
( OPC_228EUH_Block 107 OPC_228EUH_Block )
( MOMSYMBOL 125 MOMSYMBOL )
;System-Reserved Purposes:
( warning 234 wng )
( tool1 235 tl1 )
( tool0 236 tl0 )
( label 237 lbl )
( flight 238 flt )
( error 239 err )
( annotate 240 ant )
( drawing1 241 dr1 )
( drawing2 242 dr2 )
( drawing3 243 dr3 )
( drawing4 244 dr4 )
( drawing5 245 dr5 )
( drawing6 246 dr6 )
( drawing7 247 dr7 )
( drawing8 248 dr8 )
( drawing9 249 dr9 )
( boundary 250 bnd )
( pin 251 pin )
( drawing 252 drw )
( net 253 net )
( cell 254 cel )
( all 255 all )
) ;techPurposes

techLayers(
;( LayerName Layer# Abbreviation )
;( --------- ------ ------------ )
;User-Defined Layers:
( SUBSTRATE 0 SUBSTRATE )
( DIFF 1 DIFF )
( PWEL 2 PWEL )
( NWEL 3 NWEL )
( DNW 4 DNW )
( TWEL 6 TWEL )
( PWBLK 7 PWBLK )
( NATIVE 8 NATIVE )
( VTP_SP 9 VTP_SP )
( VTN_SP 10 VTN_SP )
( PPLUS 11 PPLUS )
( NPLUS 12 NPLUS )
( VT 13 VT )
( PMINUS 17 PMINUS )
( NMINUS 18 NMINUS )
( VTPHL 21 VTPHL )
( VTNI 23 VTNI )
( VTNHL 24 VTNHL )
( VTNHI 26 VTNHI )
( NPOLY 29 NPOLY )
( DEV_SP 30 DEV_SP )
( PESD 32 PESD )
( CELLEX 33 CELLEX )
( DT_CAD 34 DT_CAD )
( MG 35 MG )
( SAB 36 SAB )
( TG 37 TG )
( HR 38 HR )
( CONT 39 CONT )
( NWR 40 NWR )
( PO1 41 PO1 )
( PO0 42 PO0 )
( VARACT 43 VARACT )
( PPO_R_BLK 44 PPO_R_BLK )
( FG 45 FG )
( ME1 46 ME1 )
( VI1 47 VI1 )
( ME2 48 ME2 )
( VI2 49 VI2 )
( ME3 50 ME3 )
( VI3 51 VI3 )
( ME4 52 ME4 )
( VI4 53 VI4 )
( ME5 54 ME5 )
( VI5 55 VI5 )
( ME6 56 ME6 )
( VI6 57 VI6 )
( ME7 58 ME7 )
( VI7 59 VI7 )
( ME8 60 ME8 )
( AN 62 AN )
( C_CELL_BLOCK 63 C_CELL_BLOCK )
( MMCBP 64 MMCBP )
( MMC 65 MMC )
( TMV_RDL 66 TMV_RDL )
( AL_RDL 67 AL_RDL )
( PASV_RDL 68 PASV_RDL )
( AL_FUSE_PAD 69 AL_FUSE_PAD )
( DIFF_CAD 70 DIFF_CAD )
( PO1_CAD 71 PO1_CAD )
( M1_CAD 72 M1_CAD )
( M2_CAD 73 M2_CAD )
( M3_CAD 74 M3_CAD )
( M4_CAD 75 M4_CAD )
( M5_CAD 76 M5_CAD )
( M6_CAD 77 M6_CAD )
( M7_CAD 78 M7_CAD )
( M8_CAD 79 M8_CAD )
( NW_CAD 80 NW_CAD )
( RSYMBOL 81 RSYMBOL )
( PSYMBOL 82 PSYMBOL )
( AL_CAD 83 AL_CAD )
( NBASE 84 NBASE )
( TEXT 85 TEXT )
( SEALRMARK 86 SEALRMARK )
( FUSEMARK 88 FUSEMARK )
( FLPMARK 89 FLPMARK )
( PADMARK 90 PADMARK )
( IOID 91 IOID )
( DP 94 DP )
( SP 95 SP )
( XDIODE 96 XDIODE )
( PSUB_CAD 98 PSUB_CAD )
( SEPGND 99 SEPGND )
( SIZE 111 SIZE )
( PIXELMK 112 PIXELMK )
( FLPMARKP 115 FLPMARKP )
( INDUCTOR 116 INDUCTOR )
( IND_CAD 117 IND_CAD )
( CONT_CAD 118 CONT_CAD )
( IPWM 119 IPWM )
( ACL 120 ACL )
( PHL 121 PHL )
( SYMBOL 125 SYMBOL )
( DECODER 126 DECODER )
;System-Reserved Layers:
( Unrouted 200 Unroute )
( Row 201 Row )
( Group 202 Group )
( Cannotoccupy 203 noOcupy )
( Canplace 204 Canplac )
( hardFence 205 hardFnc )
( softFence 206 softFnc )
( y0 207 y0 )
( y1 208 y1 )
( y2 209 y2 )
( y3 210 y3 )
( y4 211 y4 )
( y5 212 y5 )
( y6 213 y6 )
( y7 214 y7 )
( y8 215 y8 )
( y9 216 y9 )
( designFlow 217 dsnFlow )
( stretch 218 stretch )
( edgeLayer 219 edgeLyr )
( changedLayer 220 chngLyr )
( unset 221 unset )
( unknown 222 unknown )
( spike 223 spike )
( hiz 224 hiz )
( resist 225 resist )
( drive 226 drive )
( supply 227 supply )
( wire 228 wire )
( pin 229 pin )
( text 230 text )
( device 231 device )
( border 232 border )
( snap 233 snap )
( align 234 align )
( prBoundary 235 prBoundary )
( instance 236 instnce )
( annotate 237 anotate )
( marker 238 marker )
( select 239 select )
( grid 251 grid )
( axis 252 axis )
( hilite 253 hilite )
( background 254 bkground )
) ;techLayers

techLayerPurposePriorities(
;layers are ordered from lowest to highest priority
;( LayerName Purpose )
;( --------- ------- )
( DIFF drawing )
( PWEL drawing )
( NWEL drawing )
( DNW drawing )
( TWEL drawing )
( VTP_SP drawing )
( VTN_SP drawing )
( PPLUS drawing )
( NPLUS drawing )
( PMINUS drawing )
( NMINUS drawing )
( VTPHL drawing )
( VTNI drawing )
( VTNHL drawing )
( VTNHI drawing )
( NPOLY drawing )
( PESD drawing )
( MG drawing )
( SAB drawing )
( TG drawing )
( HR drawing )
( CONT drawing )
( PO1 drawing )
( PO0 drawing )
( VARACT drawing )
( ME1 drawing )
( VI1 drawing )
( ME2 drawing )
( VI2 drawing )
( ME3 drawing )
( VI3 drawing )
( ME4 drawing )
( VI4 drawing )
( ME5 drawing )
( VI5 drawing )
( ME6 drawing )
( VI6 drawing )
( ME7 drawing )
( VI7 drawing )
( ME8 drawing )
( INDUCTOR drawing )
( MMCBP drawing )
( MMC drawing )
( TMV_RDL drawing )
( AL_RDL drawing )
( PASV_RDL drawing )
( AL_FUSE_PAD drawing )
( SUBSTRATE drawing )
( PWBLK drawing )
( NATIVE drawing )
( AN drawing )
( DEV_SP drawing )
( C_CELL_BLOCK drawing )
( NWR drawing )
( FG drawing )
( FUSEMARK drawing )
( SEALRMARK drawing )
( PIXELMK drawing )
( NBASE drawing )
( CELLEX drawing )
( PPO_R_BLK drawing )
( PADMARK drawing )
( IPWM drawing )
( RSYMBOL drawing )
( PSYMBOL drawing )
( FLPMARK drawing )
( FLPMARKP drawing )
( TEXT drawing )
( ACL drawing )
( PHL drawing )
( prBoundary drawing )
( DECODER drawing )
( IOID drawing )
( XDIODE drawing )
( SEPGND drawing )
( SP drawing )
( DP drawing )
( PO1_CAD TEXT )
( M1_CAD TEXT )
( M2_CAD TEXT )
( M3_CAD TEXT )
( M4_CAD TEXT )
( M5_CAD TEXT )
( M6_CAD TEXT )
( M7_CAD TEXT )
( M8_CAD TEXT )
( AL_CAD TEXT )
( PSUB_CAD TEXT )
( NW_CAD TEXT )
( DIFF_CAD TEXT )
( PWEL LL_PWELL )
( PWEL HV_PWELL )
( NWEL LL_NWELL )
( NWEL HVNW )
( NPLUS CELLSD )
( NPLUS SAS )
( VT VTP )
( VT VTN )
( VT CELL_VTN )
( VT CELL_VTP )
( VT VTPH )
( VT VTNH )
( PMINUS HVPLDD )
( NMINUS HVNLDD )
( NMINUS CELLISO )
( VT VTPL )
( VT VTNL )
( TG CELLC )
( TG ONO )
( PO1 CELLG )
( TG HVMARK )
( TG MVMARK )
( TG MVC_MARK )
( TG NT_MARK )
( CONT FGCMARK )
( NWR BFMOAT )
( SYMBOL ONOCAP )
( DT_CAD Dummy_Block )
( DIFF_CAD Dummy_Block )
( PO1_CAD Dummy_Block )
( M1_CAD Dummy_Block )
( M2_CAD Dummy_Block )
( M3_CAD Dummy_Block )
( M4_CAD Dummy_Block )
( M5_CAD Dummy_Block )
( M6_CAD Dummy_Block )
( M7_CAD Dummy_Block )
( M8_CAD Dummy_Block )
( IND_CAD Dummy_Block )
( M1_CAD Slot_Block )
( M2_CAD Slot_Block )
( M3_CAD Slot_Block )
( M4_CAD Slot_Block )
( M5_CAD Slot_Block )
( M6_CAD Slot_Block )
( M7_CAD Slot_Block )
( M8_CAD Slot_Block )
( IND_CAD Slot_Block )
( DIFF_CAD Dummy )
( PO1_CAD Dummy )
( M1_CAD Dummy )
( M2_CAD Dummy )
( M3_CAD Dummy )
( M4_CAD Dummy )
( M5_CAD Dummy )
( M6_CAD Dummy )
( M7_CAD Dummy )
( M8_CAD Dummy )
( IND_CAD Dummy )
( M1_CAD Slot )
( M2_CAD Slot )
( M3_CAD Slot )
( M4_CAD Slot )
( M5_CAD Slot )
( M6_CAD Slot )
( M7_CAD Slot )
( M8_CAD Slot )
( AL_CAD Slot )
( IND_CAD Slot )
( DIFF_CAD OPC )
( PO1_CAD OPC )
( CONT_CAD OPC )
( M1_CAD OPC )
( MMC MCAP )
( IND_CAD IND )
( CONT BAR )
( PO1 BAR )
( VI1 BAR )
( VI2 BAR )
( VI3 BAR )
( VI4 BAR )
( VI5 BAR )
( VI6 BAR )
( VI7 BAR )
( TMV_RDL BAR )
( DIFF_CAD OPC_Block )
( PO1_CAD OPC_Block )
( M1_CAD OPC_Block )
( M2_CAD OPC_Block )
( M3_CAD OPC_Block )
( M4_CAD OPC_Block )
( M5_CAD OPC_Block )
( M6_CAD OPC_Block )
( M7_CAD OPC_Block )
( M8_CAD OPC_Block )
( CONT_CAD OPC_Block )
( VI1 OPC_Block )
( VI2 OPC_Block )
( VI3 OPC_Block )
( VI4 OPC_Block )
( VI5 OPC_Block )
( VI6 OPC_Block )
( VI7 OPC_Block )
( DIFF_CAD OPC_444_Block )
( PO1_CAD OPC_444_Block )
( DIFF_CAD OPC_444LL_Block )
( PO1_CAD OPC_444LL_Block )
( DIFF_CAD OPC_228_Block )
( PO1_CAD OPC_228_Block )
( M1_CAD OPC_228_Block )
( CONT_CAD OPC_228_Block )
( DIFF_CAD OPC_228LL_Block )
( PO1_CAD OPC_228LL_Block )
( M1_CAD OPC_228LL_Block )
( CONT_CAD OPC_228LL_Block )
( DIFF_CAD OPC_466_Block )
( PO1_CAD OPC_466_Block )
( DIFF_CAD OPC_466LL_Block )
( PO1_CAD OPC_466LL_Block )
( DIFF_CAD OPC_228EUH_Block )
( PO1_CAD OPC_228EUH_Block )
( CONT_CAD OPC_228EUH_Block )
( M1_CAD OPC_228EUH_Block )
( PO1 PO_LVS )
( TMV_RDL L1_MCAP )
( TMV_RDL L1_ROUT )
( PADMARK RFPADMK )
( NWR PWR )
( SYMBOL MOMSYMBOL )
( AL_CAD Resistor_Mark )
( M1_CAD Resistor_Mark )
( M2_CAD Resistor_Mark )
( M3_CAD Resistor_Mark )
( M4_CAD Resistor_Mark )
( M5_CAD Resistor_Mark )
( M6_CAD Resistor_Mark )
( M7_CAD Resistor_Mark )
( M8_CAD Resistor_Mark )
( M1_CAD Block )
( M2_CAD Block )
( M3_CAD Block )
( M4_CAD Block )
( M5_CAD Block )
( M6_CAD Block )
( M7_CAD Block )
( M8_CAD Block )
( M1_CAD Metal_Port )
( M2_CAD Metal_Port )
( M3_CAD Metal_Port )
( M4_CAD Metal_Port )
( M5_CAD Metal_Port )
( M6_CAD Metal_Port )
( M7_CAD Metal_Port )
( M8_CAD Metal_Port )
( PADMARK BOACMK )
( PADMARK FILLERBK )
( ACL MACROMK )
( PHL FRAMMK )
( PHL BOUNDMK )
( IOID LOGO )
( SEPGND DIFFBK )
( SYMBOL MRSYMBOL )
( SYMBOL CSYMBOL )
( SYMBOL BJTSYMBOL )
( SYMBOL DSYMBOL )
( SYMBOL DIOBLK )
( SYMBOL LSYMBOL )
( SYMBOL IND_UPS )
( SYMBOL WELLBODY )
( SYMBOL MMSYMBOL )
( SYMBOL RFSYMBOL )
( SYMBOL RFMOS_S )
( SYMBOL F_MOS )
( SIZE SIZE1 )
( SIZE SIZE2 )
( SIZE SIZE3 )
( SIZE SIZE4 )
( SIZE SIZE5 )
( SIZE SIZE6 )
( SIZE SIZE7 )
( SIZE SIZE8 )
( SIZE SIZE9 )
( SIZE SIZE10 )
( SIZE SIZE11 )
( SIZE SIZE12 )
( SIZE SIZE13 )
( SIZE SIZE14 )
( SIZE SIZE15 )
( SIZE SIZE16 )
( PO1 pin )
( ME1 pin )
( ME2 pin )
( ME3 pin )
( ME4 pin )
( ME5 pin )
( ME6 pin )
( ME7 pin )
( ME8 pin )
( AL_RDL pin )
( PO1 net )
( ME1 net )
( ME2 net )
( ME3 net )
( ME4 net )
( ME5 net )
( ME6 net )
( ME7 net )
( ME8 net )
( AL_RDL net )
( PO1 boundary )
( ME1 boundary )
( ME2 boundary )
( ME3 boundary )
( ME4 boundary )
( ME5 boundary )
( ME6 boundary )
( ME7 boundary )
( ME8 boundary )
( AL_RDL boundary )
( SP SPLL1 )
( SP SP_1 )
( SP SPLL )
( DP DP2 )
( DP RF2P_1 )
( DP RF2PLL )
( SP TCAM1 )
( SP TCAM2 )
( SP CELLMARK )
( DP HD2P )
( DP RF2P )
( DP DP1 )
( SP ROM_ID )
( SP CUST_2 )
( background drawing )
( grid drawing )
( grid drawing1 )
( annotate drawing )
( annotate drawing1 )
( annotate drawing2 )
( annotate drawing3 )
( annotate drawing4 )
( annotate drawing5 )
( annotate drawing6 )
( annotate drawing7 )
( annotate drawing8 )
( annotate drawing9 )
( instance drawing )
( instance label )
( prBoundary boundary )
( prBoundary label )
( align drawing )
( hardFence drawing )
( softFence drawing )
( text drawing )
( text drawing1 )
( text drawing2 )
( border drawing )
( device drawing )
( device label )
( device drawing1 )
( device drawing2 )
( device annotate )
( wire drawing )
( wire label )
( wire flight )
( pin label )
( pin drawing )
( pin annotate )
( axis drawing )
( snap boundary )
( snap drawing )
( stretch drawing )
( y0 drawing )
( y1 drawing )
( y2 drawing )
( y3 drawing )
( y4 drawing )
( y5 drawing )
( y6 drawing )
( y7 drawing )
( y8 drawing )
( y9 drawing )
( hilite drawing )
( hilite drawing1 )
( hilite drawing2 )
( hilite drawing3 )
( hilite drawing4 )
( hilite drawing5 )
( hilite drawing6 )
( hilite drawing7 )
( hilite drawing8 )
( hilite drawing9 )
( select drawing )
( drive drawing )
( hiz drawing )
( resist drawing )
( spike drawing )
( supply drawing )
( unknown drawing )
( unset drawing )
( designFlow drawing )
( designFlow drawing1 )
( designFlow drawing2 )
( designFlow drawing3 )
( designFlow drawing4 )
( designFlow drawing5 )
( designFlow drawing6 )
( designFlow drawing7 )
( designFlow drawing8 )
( designFlow drawing9 )
( changedLayer tool0 )
( changedLayer tool1 )
( marker warning )
( marker error )
( Row drawing )
( Row label )
( Group drawing )
( Group label )
( Cannotoccupy drawing )
( Cannotoccupy boundary )
( Canplace drawing )
( Unrouted drawing )
( Unrouted drawing1 )
( Unrouted drawing2 )
( Unrouted drawing3 )
( Unrouted drawing4 )
( Unrouted drawing5 )
( Unrouted drawing6 )
( Unrouted drawing7 )
( Unrouted drawing8 )
( Unrouted drawing9 )
( edgeLayer drawing )
( edgeLayer pin )
) ;techLayerPurposePriorities

techDisplays(
;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid )
;( --------- ------- ------ --- --- --------- ------- ----- )
( DIFF drawing DIFF t t t t t )
( PWEL drawing PWEL t t t t t )
( NWEL drawing NWEL t t t t t )
( DNW drawing DNW t t t t t )
( TWEL drawing TWEL t t t t t )
( VTP_SP drawing VTP_SP t t t t t )
( VTN_SP drawing VTN_SP t t t t t )
( PPLUS drawing PPLUS t t t t t )
( NPLUS drawing NPLUS t t t t t )
( PMINUS drawing PMINUS t t t t t )
( NMINUS drawing NMINUS t t t t t )
( VTPHL drawing VTPHL t t t t t )
( VTNI drawing VTNI t t t t t )
( VTNHL drawing VTNHL t t t t t )
( VTNHI drawing VTNHI t t t t t )
( NPOLY drawing NPOLY t t t t t )
( PESD drawing PESD t t t t t )
( MG drawing MG t t t t t )
( SAB drawing SAB t t t t t )
( TG drawing TG t t t t t )
( HR drawing HR t t t t t )
( CONT drawing CONT t t t t t )
( PO1 drawing PO1 t t t t t )
( PO0 drawing PO0 t t t t t )
( VARACT drawing VARACT t t t t t )
( ME1 drawing ME1 t t t t t )
( VI1 drawing VI1 t t t t t )
( ME2 drawing ME2 t t t t t )
( VI2 drawing VI2 t t t t t )
( ME3 drawing ME3 t t t t t )
( VI3 drawing VI3 t t t t t )
( ME4 drawing ME4 t t t t t )
( VI4 drawing VI4 t t t t t )
( ME5 drawing ME5 t t t t t )
( VI5 drawing VI5 t t t t t )
( ME6 drawing ME6 t t t t t )
( VI6 drawing VI6 t t t t t )
( ME7 drawing ME7 t t t t t )
( VI7 drawing VI7 t t t t t )
( ME8 drawing ME8 t t t t t )
( INDUCTOR drawing INDUCTOR t t t t t )
( MMCBP drawing MMCBP t t t t t )
( MMC drawing MMC t t t t t )
( TMV_RDL drawing TMV_RDL t t t t t )
( AL_RDL drawing AL_RDL t t t t t )
( PASV_RDL drawing PASV_RDL t t t t t )
( AL_FUSE_PAD drawing AL_FUSE_PAD t t t t t )
( SUBSTRATE drawing SUBSTRATE t t t t t )
( PWBLK drawing PWBLK t t t t t )
( NATIVE drawing NATIVE t t t t t )
( AN drawing AN t t t t t )
( DEV_SP drawing DEV_SP t t t t t )
( C_CELL_BLOCK drawing C_CELL_BLOCK t t t t t )
( NWR drawing NWR t t t t t )
( FG drawing FG t t t t t )
( FUSEMARK drawing FUSEMARK t t t t t )
( SEALRMARK drawing SEALRMARK t t t t t )
( PIXELMK drawing PIXELMK t t t t t )
( NBASE drawing NBASE t t t t t )
( CELLEX drawing CELLEX t t t t t )
( PPO_R_BLK drawing PPO_R_BLK t t t t t )
( PADMARK drawing PADMARK t t t t t )
( IPWM drawing IPWM t t t t t )
( RSYMBOL drawing RSYMBOL t t t t t )
( PSYMBOL drawing PSYMBOL t t t t t )
( FLPMARK drawing FLPMARK t t t t t )
( FLPMARKP drawing FLPMARKP t t t t t )
( TEXT drawing TEXT t t t t t )
( ACL drawing ACL t t t t t )
( PHL drawing PHL t t t t t )
( prBoundary drawing prBoundary t t t t t )
( DECODER drawing DECODER t t t t t )
( IOID drawing IOID t t t t t )
( XDIODE drawing XDIODE t t t t t )
( SEPGND drawing SEPGND t t t t t )
( SP drawing SP t t t t t )
( DP drawing DP t t t t t )
( PO1_CAD TEXT PO1_CAD_TEXT t t t t t )
( M1_CAD TEXT M1_CAD_TEXT t t t t t )
( M2_CAD TEXT M2_CAD_TEXT t t t t t )
( M3_CAD TEXT M3_CAD_TEXT t t t t t )
( M4_CAD TEXT M4_CAD_TEXT t t t t t )
( M5_CAD TEXT M5_CAD_TEXT t t t t t )
( M6_CAD TEXT M6_CAD_TEXT t t t t t )
( M7_CAD TEXT M7_CAD_TEXT t t t t t )
( M8_CAD TEXT M8_CAD_TEXT t t t t t )
( AL_CAD TEXT AL_CAD_TEXT t t t t t )
( PSUB_CAD TEXT PSUB_CAD_TEXT t t t t t )
( NW_CAD TEXT NW_CAD_TEXT t t t t t )
( DIFF_CAD TEXT DIFF_CAD_TEXT t t t t t )
( PWEL LL_PWELL PWEL_LL_PWELL t t t t t )
( PWEL HV_PWELL PWEL_HV_PWELL t t t t t )
( NWEL LL_NWELL NWEL_LL_NWELL t t t t t )
( NWEL HVNW NWEL_HVNW t t t t t )
( NPLUS CELLSD NPLUS_CELLSD t t t t t )
( NPLUS SAS NPLUS_SAS t t t t t )
( VT VTP VT_VTP t t t t t )
( VT VTN VT_VTN t t t t t )
( VT CELL_VTN VT_CELL_VTN t t t t t )
( VT CELL_VTP VT_CELL_VTP t t t t t )
( VT VTPH VT_VTPH t t t t t )
( VT VTNH VT_VTNH t t t t t )
( PMINUS HVPLDD PMINUS_HVPLDD t t t t t )
( NMINUS HVNLDD NMINUS_HVNLDD t t t t t )
( NMINUS CELLISO NMINUS_CELLISO t t t t t )
( VT VTPL VT_VTPL t t t t t )
( VT VTNL VT_VTNL t t t t t )
( TG CELLC TG_CELLC t t t t t )
( TG ONO TG_ONO t t t t t )
( PO1 CELLG PO1_CELLG t t t t t )
( TG HVMARK TG_HVMARK t t t t t )
( TG MVMARK TG_MVMARK t t t t t )
( TG MVC_MARK TG_MVC_MARK t t t t t )
( TG NT_MARK TG_NT_MARK t t t t t )
( CONT FGCMARK CONT_FGCMARK t t t t t )
( NWR BFMOAT NWR_BFMOAT t t t t t )
( SYMBOL ONOCAP SYMBOL_ONOCAP t t t t t )
( DT_CAD Dummy_Block DT_CAD_Dummy_Block t t t t t )
( DIFF_CAD Dummy_Block DIFF_CAD_Dummy_Block t t t t t )
( PO1_CAD Dummy_Block PO1_CAD_Dummy_Block t t t t t )
( M1_CAD Dummy_Block M1_CAD_Dummy_Block t t t t t )
( M2_CAD Dummy_Block M2_CAD_Dummy_Block t t t t t )
( M3_CAD Dummy_Block M3_CAD_Dummy_Block t t t t t )
( M4_CAD Dummy_Block M4_CAD_Dummy_Block t t t t t )
( M5_CAD Dummy_Block M5_CAD_Dummy_Block t t t t t )
( M6_CAD Dummy_Block M6_CAD_Dummy_Block t t t t t )
( M7_CAD Dummy_Block M7_CAD_Dummy_Block t t t t t )
( M8_CAD Dummy_Block M8_CAD_Dummy_Block t t t t t )
( IND_CAD Dummy_Block IND_CAD_Dummy_Block t t t t t )
( M1_CAD Slot_Block M1_CAD_Slot_Block t t t t t )
( M2_CAD Slot_Block M2_CAD_Slot_Block t t t t t )
( M3_CAD Slot_Block M3_CAD_Slot_Block t t t t t )
( M4_CAD Slot_Block M4_CAD_Slot_Block t t t t t )
( M5_CAD Slot_Block M5_CAD_Slot_Block t t t t t )
( M6_CAD Slot_Block M6_CAD_Slot_Block t t t t t )
( M7_CAD Slot_Block M7_CAD_Slot_Block t t t t t )
( M8_CAD Slot_Block M8_CAD_Slot_Block t t t t t )
( IND_CAD Slot_Block IND_CAD_Slot_Block t t t t t )
( DIFF_CAD Dummy DIFF_CAD_Dummy t t t t t )
( PO1_CAD Dummy PO1_CAD_Dummy t t t t t )
( M1_CAD Dummy M1_CAD_Dummy t t t t t )
( M2_CAD Dummy M2_CAD_Dummy t t t t t )
( M3_CAD Dummy M3_CAD_Dummy t t t t t )
( M4_CAD Dummy M4_CAD_Dummy t t t t t )
( M5_CAD Dummy M5_CAD_Dummy t t t t t )
( M6_CAD Dummy M6_CAD_Dummy t t t t t )
( M7_CAD Dummy M7_CAD_Dummy t t t t t )
( M8_CAD Dummy M8_CAD_Dummy t t t t t )
( IND_CAD Dummy IND_CAD_Dummy t t t t t )
( M1_CAD Slot M1_CAD_Slot t t t t t )
( M2_CAD Slot M2_CAD_Slot t t t t t )
( M3_CAD Slot M3_CAD_Slot t t t t t )
( M4_CAD Slot M4_CAD_Slot t t t t t )
( M5_CAD Slot M5_CAD_Slot t t t t t )
( M6_CAD Slot M6_CAD_Slot t t t t t )
( M7_CAD Slot M7_CAD_Slot t t t t t )
( M8_CAD Slot M8_CAD_Slot t t t t t )
( AL_CAD Slot AL_CAD_Slot t t t t t )
( IND_CAD Slot IND_CAD_Slot t t t t t )
( DIFF_CAD OPC DIFF_CAD_OPC t t t t t )
( PO1_CAD OPC PO1_CAD_OPC t t t t t )
( CONT_CAD OPC CONT_CAD_OPC t t t t t )
( M1_CAD OPC M1_CAD_OPC t t t t t )
( MMC MCAP MMC_MCAP t t t t t )
( IND_CAD IND IND_CAD_IND t t t t t )
( CONT BAR CONT_BAR t t t t t )
( PO1 BAR PO1_BAR t t t t t )
( VI1 BAR VI1_BAR t t t t t )
( VI2 BAR VI2_BAR t t t t t )
( VI3 BAR VI3_BAR t t t t t )
( VI4 BAR VI4_BAR t t t t t )
( VI5 BAR VI5_BAR t t t t t )
( VI6 BAR VI6_BAR t t t t t )
( VI7 BAR VI7_BAR t t t t t )
( TMV_RDL BAR TMV_RDL_BAR t t t t t )
( DIFF_CAD OPC_Block DIFF_CAD_OPC_Block t t t t t )
( PO1_CAD OPC_Block PO1_CAD_OPC_Block t t t t t )
( M1_CAD OPC_Block M1_CAD_OPC_Block t t t t t )
( M2_CAD OPC_Block M2_CAD_OPC_Block t t t t t )
( M3_CAD OPC_Block M3_CAD_OPC_Block t t t t t )
( M4_CAD OPC_Block M4_CAD_OPC_Block t t t t t )
( M5_CAD OPC_Block M5_CAD_OPC_Block t t t t t )
( M6_CAD OPC_Block M6_CAD_OPC_Block t t t t t )
( M7_CAD OPC_Block M7_CAD_OPC_Block t t t t t )
( M8_CAD OPC_Block M8_CAD_OPC_Block t t t t t )
( CONT_CAD OPC_Block CONT_CAD_OPC_Block t t t t t )
( VI1 OPC_Block VI1_OPC_Block t t t t t )
( VI2 OPC_Block VI2_OPC_Block t t t t t )
( VI3 OPC_Block VI3_OPC_Block t t t t t )
( VI4 OPC_Block VI4_OPC_Block t t t t t )
( VI5 OPC_Block VI5_OPC_Block t t t t t )
( VI6 OPC_Block VI6_OPC_Block t t t t t )
( VI7 OPC_Block VI7_OPC_Block t t t t t )
( DIFF_CAD OPC_444_Block DIFF_CAD_OPC_444_Block t t t t t )
( PO1_CAD OPC_444_Block PO1_CAD_OPC_444_Block t t t t t )
( DIFF_CAD OPC_444LL_Block DIFF_CAD_OPC_444LL_Block t t t t t )
( PO1_CAD OPC_444LL_Block PO1_CAD_OPC_444LL_Block t t t t t )
( DIFF_CAD OPC_228_Block DIFF_CAD_OPC_228_Block t t t t t )
( PO1_CAD OPC_228_Block PO1_CAD_OPC_228_Block t t t t t )
( M1_CAD OPC_228_Block M1_CAD_OPC_228_Block t t t t t )
( CONT_CAD OPC_228_Block CONT_CAD_OPC_228_Block t t t t t )
( DIFF_CAD OPC_228LL_Block DIFF_CAD_OPC_228LL_Block t t t t t )
( PO1_CAD OPC_228LL_Block PO1_CAD_OPC_228LL_Block t t t t t )
( M1_CAD OPC_228LL_Block M1_CAD_OPC_228LL_Block t t t t t )
( CONT_CAD OPC_228LL_Block CONT_CAD_OPC_228LL_Block t t t t t )
( DIFF_CAD OPC_466_Block DIFF_CAD_OPC_466_Block t t t t t )
( PO1_CAD OPC_466_Block PO1_CAD_OPC_466_Block t t t t t )
( DIFF_CAD OPC_466LL_Block DIFF_CAD_OPC_466LL_Block t t t t t )
( PO1_CAD OPC_466LL_Block PO1_CAD_OPC_466LL_Block t t t t t )
( DIFF_CAD OPC_228EUH_Block DIFF_CAD_OPC_228EUH_Block t t t t t )
( PO1_CAD OPC_228EUH_Block PO1_CAD_OPC_228EUH_Block t t t t t )
( CONT_CAD OPC_228EUH_Block CONT_CAD_OPC_228EUH_Block t t t t t )
( M1_CAD OPC_228EUH_Block M1_CAD_OPC_228EUH_Block t t t t t )
( PO1 PO_LVS PO1_PO_LVS t t t t t )
( TMV_RDL L1_MCAP TMV_RDL_L1_MCAP t t t t t )
( TMV_RDL L1_ROUT TMV_RDL_L1_ROUT t t t t t )
( PADMARK RFPADMK PADMARK_RFPADMK t t t t t )
( NWR PWR NWR_PWR t t t t t )
( SYMBOL MOMSYMBOL SYMBOL_MOMSYMBOL t t t t t )
( AL_CAD Resistor_Mark AL_CAD_Resistor_Mark t t t t t )
( M1_CAD Resistor_Mark M1_CAD_Resistor_Mark t t t t t )
( M2_CAD Resistor_Mark M2_CAD_Resistor_Mark t t t t t )
( M3_CAD Resistor_Mark M3_CAD_Resistor_Mark t t t t t )
( M4_CAD Resistor_Mark M4_CAD_Resistor_Mark t t t t t )
( M5_CAD Resistor_Mark M5_CAD_Resistor_Mark t t t t t )
( M6_CAD Resistor_Mark M6_CAD_Resistor_Mark t t t t t )
( M7_CAD Resistor_Mark M7_CAD_Resistor_Mark t t t t t )
( M8_CAD Resistor_Mark M8_CAD_Resistor_Mark t t t t t )
( M1_CAD Block M1_CAD_Block t t t t t )
( M2_CAD Block M2_CAD_Block t t t t t )
( M3_CAD Block M3_CAD_Block t t t t t )
( M4_CAD Block M4_CAD_Block t t t t t )
( M5_CAD Block M5_CAD_Block t t t t t )
( M6_CAD Block M6_CAD_Block t t t t t )
( M7_CAD Block M7_CAD_Block t t t t t )
( M8_CAD Block M8_CAD_Block t t t t t )
( M1_CAD Metal_Port M1_CAD_Metal_Port t t t t t )
( M2_CAD Metal_Port M2_CAD_Metal_Port t t t t t )
( M3_CAD Metal_Port M3_CAD_Metal_Port t t t t t )
( M4_CAD Metal_Port M4_CAD_Metal_Port t t t t t )
( M5_CAD Metal_Port M5_CAD_Metal_Port t t t t t )
( M6_CAD Metal_Port M6_CAD_Metal_Port t t t t t )
( M7_CAD Metal_Port M7_CAD_Metal_Port t t t t t )
( M8_CAD Metal_Port M8_CAD_Metal_Port t t t t t )
( PADMARK BOACMK PADMARK_BOACMK t t t t t )
( PADMARK FILLERBK PADMARK_FILLERBK t t t t t )
( ACL MACROMK ACL_MACROMK t t t t t )
( PHL FRAMMK PHL_FRAMMK t t t t t )
( PHL BOUNDMK PHL_BOUNDMK t t t t t )
( IOID LOGO IOID_LOGO t t t t t )
( SEPGND DIFFBK SEPGND_DIFFBK t t t t t )
( SYMBOL MRSYMBOL SYMBOL_MRSYMBOL t t t t t )
( SYMBOL CSYMBOL SYMBOL_CSYMBOL t t t t t )
( SYMBOL BJTSYMBOL SYMBOL_BJTSYMBOL t t t t t )
( SYMBOL DSYMBOL SYMBOL_DSYMBOL t t t t t )
( SYMBOL DIOBLK SYMBOL_DIOBLK t t t t t )
( SYMBOL LSYMBOL SYMBOL_LSYMBOL t t t t t )
( SYMBOL IND_UPS SYMBOL_IND_UPS t t t t t )
( SYMBOL WELLBODY SYMBOL_WELLBODY t t t t t )
( SYMBOL MMSYMBOL SYMBOL_MMSYMBOL t t t t t )
( SYMBOL RFSYMBOL SYMBOL_RFSYMBOL t t t t t )
( SYMBOL RFMOS_S SYMBOL_RFMOS_S t t t t t )
( SYMBOL F_MOS SYMBOL_F_MOS t t t t t )
( SIZE SIZE1 SIZE_SIZE1 t t t t t )
( SIZE SIZE2 SIZE_SIZE2 t t t t t )
( SIZE SIZE3 SIZE_SIZE3 t t t t t )
( SIZE SIZE4 SIZE_SIZE4 t t t t t )
( SIZE SIZE5 SIZE_SIZE5 t t t t t )
( SIZE SIZE6 SIZE_SIZE6 t t t t t )
( SIZE SIZE7 SIZE_SIZE7 t t t t t )
( SIZE SIZE8 SIZE_SIZE8 t t t t t )
( SIZE SIZE9 SIZE_SIZE9 t t t t t )
( SIZE SIZE10 SIZE_SIZE10 t t t t t )
( SIZE SIZE11 SIZE_SIZE11 t t t t t )
( SIZE SIZE12 SIZE_SIZE12 t t t t t )
( SIZE SIZE13 SIZE_SIZE13 t t t t t )
( SIZE SIZE14 SIZE_SIZE14 t t t t t )
( SIZE SIZE15 SIZE_SIZE15 t t t t t )
( SIZE SIZE16 SIZE_SIZE16 t t t t t )
( PO1 pin PO1_pin t t t t t )
( ME1 pin ME1_pin t t t t t )
( ME2 pin ME2_pin t t t t t )
( ME3 pin ME3_pin t t t t t )
( ME4 pin ME4_pin t t t t t )
( ME5 pin ME5_pin t t t t t )
( ME6 pin ME6_pin t t t t t )
( ME7 pin ME7_pin t t t t t )
( ME8 pin ME8_pin t t t t t )
( AL_RDL pin AL_RDL_pin t t t t t )
( PO1 net PO1_net t t t t t )
( ME1 net ME1_net t t t t t )
( ME2 net ME2_net t t t t t )
( ME3 net ME3_net t t t t t )
( ME4 net ME4_net t t t t t )
( ME5 net ME5_net t t t t t )
( ME6 net ME6_net t t t t t )
( ME7 net ME7_net t t t t t )
( ME8 net ME8_net t t t t t )
( AL_RDL net AL_RDL_net t t t t t )
( PO1 boundary PO1_boundary t t t t t )
( ME1 boundary ME1_boundary t t t t t )
( ME2 boundary ME2_boundary t t t t t )
( ME3 boundary ME3_boundary t t t t t )
( ME4 boundary ME4_boundary t t t t t )
( ME5 boundary ME5_boundary t t t t t )
( ME6 boundary ME6_boundary t t t t t )
( ME7 boundary ME7_boundary t t t t t )
( ME8 boundary ME8_boundary t t t t t )
( AL_RDL boundary AL_RDL_boundary t t t t t )
( SP SPLL1 SP_SPLL1 t t t t t )
( SP SP_1 SP_SP_1 t t t t t )
( SP SPLL SP_SPLL t t t t t )
( DP DP2 DP_DP2 t t t t t )
( DP RF2P_1 DP_RF2P_1 t t t t t )
( DP RF2PLL DP_RF2PLL t t t t t )
( SP TCAM1 SP_TCAM1 t t t t t )
( SP TCAM2 SP_TCAM2 t t t t t )
( SP CELLMARK SP_CELLMARK t t t t t )
( DP HD2P DP_HD2P t t t t t )
( DP RF2P DP_RF2P t t t t t )
( DP DP1 DP_DP1 t t t t t )
( SP ROM_ID SP_ROM_ID t t t t t )
( SP CUST_2 SP_CUST_2 t t t t t )
( background drawing background t nil t nil nil )
( grid drawing grid t nil t nil nil )
( grid drawing1 grid1 t nil t nil nil )
( annotate drawing annotate t t t t nil )
( annotate drawing1 annotate1 t t t t nil )
( annotate drawing2 annotate2 t t t t nil )
( annotate drawing3 annotate3 t t t t nil )
( annotate drawing4 annotate4 t t t t nil )
( annotate drawing5 annotate5 t t t t nil )
( annotate drawing6 annotate6 t t t t nil )
( annotate drawing7 annotate7 t t t t nil )
( annotate drawing8 annotate8 t t t t nil )
( annotate drawing9 annotate9 t t t t nil )
( instance drawing instance t t t t nil )
( instance label instanceLbl t t t t nil )
( prBoundary boundary prBoundaryBnd t t t t nil )
( prBoundary label prBoundaryLbl t t t t nil )
( align drawing defaultPacket t t t t nil )
( hardFence drawing hardFence t t t t nil )
( softFence drawing softFence t t t t nil )
( text drawing text t t t t nil )
( text drawing1 text1 t t t t nil )
( text drawing2 text2 t t t t nil )
( border drawing border t t t t nil )
( device drawing device t t t t nil )
( device label deviceLbl t t t t nil )
( device drawing1 device1 t t t t nil )
( device drawing2 device2 t t t t nil )
( device annotate deviceAnt t t t t nil )
( wire drawing wire t t t t nil )
( wire label wireLbl t t t t nil )
( wire flight wireFlt t t t t nil )
( pin label pinLbl t t t t nil )
( pin drawing pin t t t t nil )
( pin annotate pinAnt t t t t nil )
( axis drawing axis t nil t t nil )
( snap boundary snap t t t t nil )
( snap drawing snap t t t t nil )
( stretch drawing stretch t t t t nil )
( y0 drawing y0 t t t t nil )
( y1 drawing y1 t t t t nil )
( y2 drawing y2 t t t t nil )
( y3 drawing y3 t t t t nil )
( y4 drawing y4 t t t t nil )
( y5 drawing y5 t t t t nil )
( y6 drawing y6 t t t t nil )
( y7 drawing y7 t t t t nil )
( y8 drawing y8 t t t t nil )
( y9 drawing y9 t t t t nil )
( hilite drawing hilite t t t t nil )
( hilite drawing1 hilite1 t t t t nil )
( hilite drawing2 hilite2 t t t t nil )
( hilite drawing3 hilite3 t t t t nil )
( hilite drawing4 hilite4 t t t t nil )
( hilite drawing5 hilite5 t t t t nil )
( hilite drawing6 hilite6 t t t t nil )
( hilite drawing7 hilite7 t t t t nil )
( hilite drawing8 hilite8 t t t t nil )
( hilite drawing9 hilite9 t t t t nil )
( select drawing select t t t t nil )
( drive drawing drive t t t t nil )
( hiz drawing hiz t t t t nil )
( resist drawing resist t t t t nil )
( spike drawing spike t t t t nil )
( supply drawing supply t t t t nil )
( unknown drawing unknown t t t t nil )
( unset drawing unset t t t t nil )
( designFlow drawing designFlow t nil nil nil nil )
( designFlow drawing1 designFlow1 t nil nil nil nil )
( designFlow drawing2 designFlow2 t nil nil nil nil )
( designFlow drawing3 designFlow3 t nil nil nil nil )
( designFlow drawing4 designFlow4 t nil nil nil nil )
( designFlow drawing5 designFlow5 t nil nil nil nil )
( designFlow drawing6 designFlow6 t nil nil nil nil )
( designFlow drawing7 designFlow7 t nil nil nil nil )
( designFlow drawing8 designFlow8 t nil nil nil nil )
( designFlow drawing9 designFlow9 t nil nil nil nil )
( changedLayer tool0 changedLayerTl0 nil nil t nil nil )
( changedLayer tool1 changedLayerTl1 nil nil t nil nil )
( marker warning markerWarn t t t t nil )
( marker error markerErr t t t t nil )
( Row drawing Row t t t t nil )
( Row label RowLbl t t t t nil )
( Group drawing Group t t t t nil )
( Group label GroupLbl t t t t nil )
( Cannotoccupy drawing Cannotoccupy t t t t nil )
( Cannotoccupy boundary CannotoccupyBnd t t t t nil )
( Canplace drawing Canplace t t t t nil )
( Unrouted drawing Unrouted t t t t nil )
( Unrouted drawing1 Unrouted1 t t t t nil )
( Unrouted drawing2 Unrouted2 t t t t nil )
( Unrouted drawing3 Unrouted3 t t t t nil )
( Unrouted drawing4 Unrouted4 t t t t nil )
( Unrouted drawing5 Unrouted5 t t t t nil )
( Unrouted drawing6 Unrouted6 t t t t nil )
( Unrouted drawing7 Unrouted7 t t t t nil )
( Unrouted drawing8 Unrouted8 t t t t nil )
( Unrouted drawing9 Unrouted9 t t t t nil )
( edgeLayer drawing edgeLayer t t t t nil )
( edgeLayer pin edgeLayerPin t t t t nil )
) ;techDisplays

techLayerProperties(
;( PropName Layer1 [ Layer2 ] PropValue )
)

) ;layerDefinitions


;********************************
; LAYER RULES
;********************************
layerRules(

streamLayers(
;( layer streamNumber dataType translate )
;( ----- ------------ -------- --------- )
( ("DIFF" "drawing") 1 0 t )
( ("PWEL" "drawing") 2 0 t )
( ("PWEL" "LL_PWELL") 2 1 t )
( ("PWEL" "HV_PWELL") 2 2 t )
( ("NWEL" "drawing") 3 0 t )
( ("NWEL" "LL_NWELL") 3 1 t )
( ("NWEL" "HVNW") 3 2 t )
( ("DNW" "drawing") 4 0 t )
( ("TWEL" "drawing") 6 0 t )
( ("VTP_SP" "drawing") 9 0 t )
( ("VTN_SP" "drawing") 10 0 t )
( ("PPLUS" "drawing") 11 0 t )
( ("NPLUS" "drawing") 12 0 t )
( ("NPLUS" "CELLSD") 12 1 t )
( ("NPLUS" "SAS") 12 2 t )
( ("VT" "VTP") 13 0 t )
( ("VT" "VTN") 14 0 t )
( ("VT" "CELL_VTN") 25 0 t )
( ("VT" "CELL_VTP") 25 36 t )
( ("VT" "VTPH") 15 0 t )
( ("VT" "VTNH") 16 0 t )
( ("PMINUS" "drawing") 17 0 t )
( ("PMINUS" "HVPLDD") 17 1 t )
( ("NMINUS" "drawing") 18 0 t )
( ("NMINUS" "HVNLDD") 15 71 t )
( ("NMINUS" "CELLISO") 18 3 t )
( ("VT" "VTPL") 20 0 t )
( ("VTPHL" "drawing") 21 0 t )
( ("VT" "VTNL") 22 0 t )
( ("VTNI" "drawing") 23 0 t )
( ("VTNHL" "drawing") 24 0 t )
( ("VTNHI" "drawing") 26 0 t )
( ("NPOLY" "drawing") 29 0 t )
( ("PESD" "drawing") 32 0 t )
( ("MG" "drawing") 35 0 t )
( ("SAB" "drawing") 36 0 t )
( ("TG" "drawing") 37 0 t )
( ("TG" "CELLC") 37 1 t )
( ("TG" "ONO") 37 2 t )
( ("HR" "drawing") 38 0 t )
( ("CONT" "drawing") 39 0 t )
( ("PO1" "drawing") 41 0 t )
( ("PO0" "drawing") 41 1 t )
( ("PO1" "CELLG") 41 2 t )
( ("VARACT" "drawing") 43 0 t )
( ("ME1" "drawing") 46 0 t )
( ("VI1" "drawing") 47 0 t )
( ("ME2" "drawing") 48 0 t )
( ("VI2" "drawing") 49 0 t )
( ("ME3" "drawing") 50 0 t )
( ("VI3" "drawing") 51 0 t )
( ("ME4" "drawing") 52 0 t )
( ("VI4" "drawing") 53 0 t )
( ("ME5" "drawing") 54 0 t )
( ("VI5" "drawing") 55 0 t )
( ("ME6" "drawing") 56 0 t )
( ("VI6" "drawing") 57 0 t )
( ("ME7" "drawing") 58 0 t )
( ("VI7" "drawing") 59 0 t )
( ("ME8" "drawing") 60 0 t )
( ("INDUCTOR" "drawing") 60 36 t )
( ("MMCBP" "drawing") 64 0 t )
( ("MMC" "drawing") 65 0 t )
( ("TMV_RDL" "drawing") 66 0 t )
( ("AL_RDL" "drawing") 67 0 t )
( ("PASV_RDL" "drawing") 68 0 t )
( ("AL_FUSE_PAD" "drawing") 69 0 t )
( ("SUBSTRATE" "drawing") 0 0 t )
( ("PWBLK" "drawing") 7 0 t )
( ("NATIVE" "drawing") 7 36 t )
( ("AN" "drawing") 8 36 t )
( ("DEV_SP" "drawing") 9 16 t )
( ("C_CELL_BLOCK" "drawing") 25 72 t )
( ("TG" "HVMARK") 37 3 t )
( ("TG" "MVMARK") 37 4 t )
( ("TG" "MVC_MARK") 37 7 t )
( ("TG" "NT_MARK") 37 8 t )
( ("CONT" "FGCMARK") 39 1 t )
( ("NWR" "drawing") 40 0 t )
( ("NWR" "BFMOAT") 40 1 t )
( ("FG" "drawing") 41 8 t )
( ("FUSEM

layername purpose packet

It finally worked

It was solved when I posted my problem on:
https://groups.google.com/group/comp.cad.cadence/browse_thread/thread/ee2b2c1a2f9b0f74#

The number of display levels, 'stop' was set to zero by default! I set it to 99 and it worked.

how to use opc_block layer

hassaneldib said:

I can see the transistors layouts when designing the layout of a transistor level design. But at the top-level layout design, when i come to connect the designed layouts, i only see empty boxes.

Please, can you tell me how can i view the layout contents of the instances instead of empty boxes?
I tried pressing SHIFT-F but it did not work.

Click to expand...

options---->display------>display levels--->start 0 and stop 32