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How to draw antenna diode to protect mosfet from antenna effect?

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henrywent

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hi there,
how to draw antenna diode to protect mosfet from antenna effect. I don't see any diode pcell dedicated to this purpose. Can we use normal diode pcell from the PDK to achieve the function. ANY LINK OR DOCUMENT IS WELCOMED! Thanks in advance!
 

antenna diode

Hi

If I am not mistaken, you can use a standard diode to avoid antenna effect. Or just change metal layers near the poly to avoid damage on the gates.
 

    H

    henrywent

    Points: 2
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anteena diodes

Hi,

If the violations number is not large, you can change the metal route layer to solve this problem. (prefer to change it as upper level metal/via layer)
 

    H

    henrywent

    Points: 2
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antenna diode+antenna violation

Hi,
Well usually antenna diodes are created using the NMOS available in the PDK. Just short the source and the drain of the NMOS and connect it to the signal. While the Gate has to be grounded...

signal >---------------
s| | d
|____|
-------
g |
|
GND

The width of the NMOS can be 3 to 5 times the minumum width, which helps to overcome the gate to metal ratio of the antenna violation.

Hope this helps...
 

    H

    henrywent

    Points: 2
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antenna diode +layer jumping

Goldeneagle said:
Hi,
... Just short the source and the drain of the NMOS and connect it to the signal. While the Gate has to be grounded...

signal >---------------
s| | d
|____|
-------
g |
|
GND

Hope this helps...
Click to expand...
Don't think so. Isn't this a cap, rather than a diode? ;-)
 

antenna diode effect

erikl said:
Don't think so. Isn't this a cap, rather than a diode? ;-)
Click to expand...

If I am not wrong, the Source and the Drain act as the diffusion diodes to sink in the extra charges due to the antenna effect. Connecting the gate to ground avoids the channel formation.
Taking a small metal jump to the higher level is the first step that should be tried, rather than adding antenna diodes which leads to reverse bias leakages (and especially on the switching nodes).
 

antenna diode on analog signals

ravirajdv said:
... If I am not wrong, the Source and the Drain act as the diffusion diodes to sink in the extra charges due to the antenna effect.
Click to expand...
Yes, this is true; I forgot the bulk diode effect. This diode would "swallow" negative charges. Ion etching, however, delivers positive charges. So a p+ in nwell diode - or a PMOS - should be used (nwell connected to VDD). During metal etch, the nwell is close to GND potential.
 

+nmos diode

erikl said:
ravirajdv said:
... If I am not wrong, the Source and the Drain act as the diffusion diodes to sink in the extra charges due to the antenna effect.
Click to expand...
Yes, this is true; I forgot the bulk diode effect. This diode would "swallow" negative charges. Ion etching, however, delivers positive charges. So a p+ in nwell diode - or a PMOS - should be used (nwell connected to VDD). During metal etch, the nwell is close to GND potential.
Click to expand...

Hi erikl,
Are NMOS devices not sufficient?
I have not seen anybody using the PMOS devices in addition.
Reasons:
1> Since it is connected to VDD, more reverse bias leakage.
2> More area.

Do you see any other reasons, Process issues? (please throw some light)

Regards,
RDV
 

antenna diode edaboard

erikl said:
Ion etching, however, delivers positive charges. So a p+ in nwell diode - or a PMOS - should be used (nwell connected to VDD).
Click to expand...

ravirajdv said:
Hi erikl, Are NMOS devices not sufficient?
Click to expand...
An n+ on p diode won't avoid the build-up of a positive voltage level possibly high enough to destroy the gate oxide.

ravirajdv said:
I have not seen anybody using the PMOS devices in addition.
Click to expand...
Not necessarily in addition. NMOS diode only. I did! ;-)

ravirajdv said:
Reasons:
1> Since it is connected to VDD, more reverse bias leakage.
Click to expand...
Why? I don't see a reason for this.

ravirajdv said:
2> More area.
Click to expand...
Minimum allowed area is sufficient for an antenna diode.

ravirajdv said:
Do you see any other reasons, Process issues? (please throw some light)
Regards,
RDV
Click to expand...
Hi RDV, pls. s. my reason above. Process issue: yes! The etching ions are charged positively (as ions use to be ;-) ), so obviously they tend to build up positive voltage levels rather than negative ones.
Cheers, erikl
 

antenna diode size

erikl said:
erikl said:
Ion etching, however, delivers positive charges. So a p+ in nwell diode - or a PMOS - should be used (nwell connected to VDD).
Click to expand...

ravirajdv said:
Hi erikl, Are NMOS devices not sufficient?
Click to expand...
An n+ on p diode won't avoid the build-up of a positive voltage level possibly high enough to destroy the gate oxide.

ravirajdv said:
I have not seen anybody using the PMOS devices in addition.
Click to expand...
Not necessarily in addition. NMOS diode only. I did! ;-)

ravirajdv said:
Reasons:
1> Since it is connected to VDD, more reverse bias leakage.
Click to expand...
Why? I don't see a reason for this.

ravirajdv said:
2> More area.
Click to expand...
Minimum allowed area is sufficient for an antenna diode.

ravirajdv said:
Do you see any other reasons, Process issues? (please throw some light)
Regards,
RDV
Click to expand...
Hi RDV, pls. s. my reason above. Process issue: yes! The etching ions are charged positively (as ions use to be ;-) ), so obviously they tend to build up positive voltage levels rather than negative ones.
Cheers, erikl
Click to expand...

Hey erikl,
By more leakage I mean, the NWELL is tied to VDD and hence the reverse biased diode so formed with the substrate will have the reverse biased current. If there is a nmos, we can avoid this.
By more area I mean, compared to the nmos device pmos device would take more area because of the nwell.
Thanks.
Regards,
RDV
 

antenna gate diffusion area

ravirajdv said:
Hey erikl,
By more leakage I mean, the NWELL is tied to VDD and hence the reverse biased diode so formed with the substrate will have the reverse biased current. If there is a nmos, we can avoid this.
By more area I mean, compared to the nmos device pmos device would take more area because of the nwell.
Thanks.
Regards,
RDV
Click to expand...
Hi RDV,
the reverse current of a p+ on nwell diode is not determined by the nwell area, but by the area of the p+ diffusion (in the nwell), and this can be the minimum area allowed by DRC rules. Hence the reverse current shouldn't be greater than that of a minimum size n+ on substrate diode.
Cheers, erikl
 

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