wylee
Full Member level 1
Does anyone knows how to design a biasing voltage reference circuit with enable/disable function in CMOS?
Normal stable biasing reference point are generated from a chain of equal size PMOS loads. How can we improved this with a enable/disable circuitary which is stable in process and temperature variations? :?:
Normal stable biasing reference point are generated from a chain of equal size PMOS loads. How can we improved this with a enable/disable circuitary which is stable in process and temperature variations? :?: