The value of the pull-down resistor question

why pulldown what value

For the diagram attached the following text is mentioned in a book:
"The value of the pull-down resistor should be high enough to limit the power consumption of the circuit but low enough to create a voltage that is comfortably below the driven circuits logic-0 threshold"
I donot understand why the vlaue of pull down should be low enough. Whatever may be the value of resistor(except 0) the voltage would be input minus diode drop voltage. Then how a low value of resistor instead of high value resistor could create a voltage that is below the driven circuits logic-0 threshold.

pulldown value

The question can't be answered without considering the specification of the connected logic families. It actually works with many of them. The low enough discussion is only understandable when you know, that logic families as TTL have an input current.

Re: pulldown value

What happens if it is connected to TTL input. How does the resistor impact current drawn by TTL gate?

Re: pulldown value

I think it is something like this:

1. Condition 1:

When either one of the inputs are high the output is supposed to be high. In this condition the forward resistance of the diode must be smaller than the pull down resistor to allow the output voltage to rise sufficiently high.

2. Condition 2:

When both the inputs are low the output is supposed to be low. Under this condition if the following stage is to be driven, it needs some minimum current to flow through the pulldown resistor to make the following stage work. If the resistor is very high, the drop across it due to the A=0, B=0 current may be high enough to turn the output high for the next stage. So the pull down resistor is to be low enough to improve this noise margin.

It is therefore a trade-off between proper o/p level and improvement in noise margin.

Re: pulldown value

Thanks Subharpe and FvM.
I have another query regarding this. Whenever there is a logic 0 input to the TTL family, there is some base current that is flowing out of the gate. Is it the reverse bias current or the current out of a PNP transitor? Is there any brief material that details about the TTL logic family?

Added after 42 minutes:

Got information at: https://en.wikipedia.org/wiki/Transistor-transistor_logic

pulldown value

The input of an old TTL gate is the emitter of an NPN transistor. Its max current when low is 1.6mA. LS-TTL is different.
0.4V is a good valid logic low voltage so the value of the pulldown resistor should be 0.4V/1.6mA= 250 ohms.