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shared variables in VHDL

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booblik

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shared variable vhdl

What is the use of shared variables in VHDL, if they cannot be synthesized?
Why would someone write non-synthesizable code?
 

non-synthesizable vhdl

Hi,
>>What is the use of shared variables in VHDL, if they cannot be synthesized?
>>Why would someone write non-synthesizable code?


Generally variables are used or can be used in a particular process.It is dedicated to only that process.But Shared variable are those which can be used in more than one process.However,when one process is using the shared varible other process should not use it.

Non-synthesizable code is written for testing and simulation.Through simulation one can know how the program runs.

I hope I am clear.
 

vhdl shared variable example

Hi Tan,

Thanks for you answer.

So in a real environment, a simulation would be written first, the program tested and understood and then non-synthesizables code would be rewritten to make it synthesizable?
 

vhdl shared variables

Hmmm..
See for example if you want to check real numbers.You have to simulate the code to just see the result.But the real numbers are not synthesizable at all..
There are some codes which are not synthesizable but you want to see the result..then simulation helps.we can simulate and check the result.

I hope You understood.
 

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    booblik

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vhdl+test+bench+shared+variable

and then non-synthesizables code would be rewritten to make it synthesizable?
Click to expand...
Most likely, no code will be rewritten. In VHDL simulation, a testbench is placed around the top entity of the tested code, interfacing it's ports. The testbench code is used only in simulation, it can contain all kinds of nonsynthesizable VHDL elements, e.g. textio, real numbers and similar. I have testbenches, where analog signals in a process are modelled through difference equations, generating simulated ADC signals that are send to the simulated code.
 

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