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Initialisation of Array in VHDL

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oursriharsha

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create a array of hexadecimal numbers in vhdl

type VECTOR_MEM is array (23 downto 0) of std_logic_vector(9 downto 0); -- 8x8
signal INSTR_VECTOR : VECTOR_MEM; -- 24 X10 locations.

can anyone please tell me how to initialise these values with a predefined set of vectors.

-- while accessing these locations can i access them as
Vector(addr)

addr being incremented .


How is this operation synthesized.

Regards
 

initialising memory array in vhdl

Hi,
You can declare them in an LUT and call one by one.
In that way you can pre-define the array.
 

vhdl memory block mif

can u Please throw more light doing the same .

rgds

Added after 2 hours 7 minutes:

hello any replies ..?

-- i have followed this procedure ,
Code: 
VECTOR(0) <= "0000000000";
Vector(1) <= "1001000000";
VECTOR(2) <= "0001000000";
Vector(3) <= "0011000000";
--
VECTOR(4) <= "0000000111";
Vector(5) <= "1001001100";
VECTOR(6) <= "0001110000";
Vector(7) <= "0011110000";

but i dont feel this is worth making as my bits goes on increasing .

--- please give me idea of writing to an LUT
 

vhdl array hex

Hi,
I declared in this way and it worked.

"type lut is array (0 to 31) of std_logic_vector(7 downto 0);"


signal downshift :lut:=(x"44",x"6f",x"77",x"6e",x"73",x"68",x"69",X"66",X"74",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",x"20",x"20");

In the above statement,I have predefined DOWNSHIFT lut.In the Brackets I have written the hexadecimal numbers which define alphabets.
Where X"44" means D...

I hope this time I am clear.

Tan
 
vhdl vector initialisation

If you know the array (memory) size that you need, then you can use Altera's Megawizard or Xilinx Coregen to generate a RAM BLOCK and use it in your design.

When you create the RAM Block, you will see options to initialize the block via .HEX or .MIF files. You can generate these files and then use them to initialize the memory block on power-up. This works when you want to validate the design on the demo/ FPGA board.
 

how to create a lut with vhdl

My requirement is not use the RAM for the same , as the vector length is not fixed .

can u please help me further in this similar grounds in my other post ..?

Added after 45 seconds:
 

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