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I've done it, but i think you'd better do your job yourself unless you're going to pay for it. Anyway I am summarizing my job (Implementation of an HDLC transceiver with FPGA) in a paper. As soon as I could prepare it, I'll send it to you.
it is not working properly..
In Open cores hdlc code... last byte is getting repeated in the transmission that to for 7 bits ..
In the Project post.. Test bench data is woring fine.. If i transmit 0xFF, 0 xFF, 0x01, 0x00 then the result is 0xFF, 0xFF, 0x00, 0x00.
Any one have faced these problems??
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