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clock signal in a latch comparator

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kickbeer

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clock generator ltspice

helllo everyone,

I'm still not confident about this.For one cycle of clock signal, the comparator compares the inputs once.two cycles means the comparator compares the input twice. Am i right? can somebody correct my statement?
thx in adv
 

latch comparator with reset

In a clocked latch comparator, in a half of the clock cycle, the comparator does the comparison. In order words, at the end of that half clock cycle, the results of the comparison is at the output of the comparator.
In the other half cycle, the comparator is reset and gets ready for the next comparison. This half cycle is called reset phase.

OpAmp
 

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    kickbeer

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OpAmp said:
In a clocked latch comparator, in a half of the clock cycle, the comparator does the comparison. In order words, at the end of that half clock cycle, the results of the comparison is at the output of the comparator.
In the other half cycle, the comparator is reset and gets ready for the next comparison. This half cycle is called reset phase.

OpAmp
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hello OpAmp,

To configure the VPULSE as clock generator in LTSpice, do we need formula to get the right frequency or we try to simulate different values until we get the right output??
 

hello OpAmp,

To configure the VPULSE as clock generator in LTSpice, do we need formula to get the right frequency or we try to simulate different values until we get the right output??[/quote

Comparator operates at its frequency specifications. If you are designing a comparator then it should operate at your required clock frequency. So your approach should be to debug the circuit and find out the error rather than changing different values in vpulse.

Let me know what frequency you are trying to operate at. I will try simulating the same in my LTSpice and let you know ...
 

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    kickbeer

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hi sanredrose,

The frequency i'm trying now is 1 MHz
 

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