i2c fsm designing doubts - what is debouncing circuit in I2C

i2c fsm designing

Hello all,
i was studying I2c slave specification.I noticed there are 2 clk in one is SCL and other is system CLK. My doubt is i saw a code on open core and i found they were registering data on System clk rather SCL.
what is debouncing circuit in I2C?
thanks in advance!

i2c debounce

can any one help on this?

i2c glitch

debouncing circuit is used to remove the gitch of SCL .

I2c doubts

Thanks heartfree,
Do u have any documents for debouncing circuit of I2C or can you please elaborate it?

Re: I2c doubts

you can see the spec of I2c to investigate !

Re: I2c doubts

@heartfree
Can you explain more about de-bouncing circuit usage in I2C ???

I2c doubts

System clock is generally faster than SCL. We can use system clock to measure the width of SDA or SCL, for example ,if the width is larger then 8cycle of system clock, that means that SDA and SCL is stable and the transistion is not glitch.

Re: I2c doubts

Deboucing circuit is not required in all the cases.Mostly debouncing is required in FPGA.In Asic's Mostly the SDA And SCL input should be made spike free by using schmit switch..

I2c doubts

Yes. Bus clocked I2C slave interfaces mainly need some precautions against false double clocking from ringing edges. Industry standard devices are said to have e.g. 50 ns spike filtering, typically achiedved by a schmitt trigger.

Re: I2c doubts

heartfree is full of it with his debouncing BS. There is no such thing in I2C. The clk as some people already mentioned is a real free running clock used for system tasks. For example it clocks your flops in the state machine and the interface logic. SCL is not really a clock since it does not run all the time and is used by both I2C slave and master to stop each other from transmitting data. Some type of wait state. So, you see, it can not be used as a normal, always running clock by the rest of your logic.

I wish those who don't know would stop posting BS to rack up their points.

Re: I2c doubts

As far as I see, there are two types of I2C slave interfaces: Complex peripherals, that utilize a system clock and simple asynchronous ones without it. If a system clock is present, you won't treat SCL as a clock rather processing the I2C signals synchronously. Up to medium system clock speeds, no debouncing logic is necessary, as rakko stated. (Personally I prefer to ignore meaningless contributions rather than commenting them or using strong words about it. You mainly get points for helping people, and the originator has to decide, if your answer is helpful somehow.)

But there are also simple I2C interfaces without a system clock. They have to process SCL and possibly SDA by edge sensitive circuits and typically use debouncing circuits. I can imagine several applications, where CPLD based I2C slave designs of this type are suitable.

Re: I2c doubts

Thanks Rakko, FVM for your KS.
As we will use schmit switch on our SDA and SCL input of I2C slave I am not going to debounce the SDA, SCL anymore. My slave is running at 1MHZ Fast mode plus but still i think I don't need Deboucing circuit .Deboucing ckt is required in FPGA because i guess there is no Schmidt switch implemented on its inputs.