Structures to match devices

matching layout well proximity effect

Hi

I have been working in layout for a couple of years and I am familiar with a number of techniques for matching devices. As is commonly recomended I try and keep matching devices

- Close to each other
- Orientated in the same direction
- Protected by dummy devices
- Interdigitated / Cross quaded as required

I have recently started in a new position and a number of designers like their diff pairs / current mirrors laid out in different structures to what I'm used to. Using a simple two transistor current mirror as an example commonly I would use abutment to create a tight layout and allow the dummy devices to share the diffusion meaning the 'working devices' were fairly well protected from STI effects (example 1 in picture; poly - red rectanges, diffusion - green rectangles, metal 1 - blue lines, metal 2 - green lines, black spots - contacts).

However some of the designers prefer a structure like 2, where the devices are flipped through 90 degrees, as they feel this allows better current flow (I have no doubt it does). However this structure does not allow the 'working' devices to be protected from STI effects, and although they should all undergo similar ammounts of STI stress due to the dummy devices I dont think this will be a particulary well matched mirror.

I don't want to rule second structure out of hand without doing a bit of research so if the second structure is just as good, or indeed better I would appreciate some feedback. Should you need any further information let us know, we are using a 130nm process, i have been using this for sometime however I believe the designers are used to larger geometries.

Should anyone have any questions please let me know, many thanks

layout techniques to reduce lod effect

Has no one any thoughts on this?

lod and well proximity effect

Pat,

Please go through LOD(lenght of Diffusion) effect that becomes prevelent below 90nm.
To keep Sa and Sb same for every transistor your new company is using structure like 2.

Thanks for the reply.

My understanding was that big value of sa and sb were more important than equal values, ie that although sa and sb were matched in layout 2 the stresses they produced would severely affect device matching, and so layout 1 would be a better option. I will read more into LOD effects, can anyone recomend good papers or books?

Pat,
Now you are talking about well proximity effect . This is sth different where gate should be som far from well edge( pls correct me if I am wrong)......
Generally the device you get from process the diffusion well is already; extended from diffusion edge which takes care of this effect..

I understand about the well proximity effect and your understanding of it is the same as mine that matched devices should not be placed close (within 2 or 3 um) to the nwell / substrate boundary.
What I meant was in the picture above the devices A and B in structure 1 were protected from STI effects by the dummy devices at either end. However in structure 2 each device would be exposed to STI stresses along every boundary, and my understanding thus far had been that having big values of sa and sb (ie having gates far away from the active / sti junction) was more important than having equal values of sa and sb.

you are right.. I missed that point earlier..

I assumed dummy is present on either side of each transistor to reduce STI stress effect... but actually it is not.....to my surprise..