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Clock Tree Synthesis : Sink Reports

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clock tree sink

In CTS terminology, What do we mean by "Sink Reports"? How do we report them in Magma/Synopsys tools? What is the significance of these reports?

Thanks!
 

how to understand the clock tree from report

Hi

Sink reports mean the reports of design objects where your clock is being consumed
These design objects can be flip flops , latches , clock gating cells etc.
In STA every endpoint of a path is considered as a sink of clock tree..
 
Sinks are nothing but the clock tree end points.The distribution of sinks across the design plays an important role in getting skew to zero for a clock domain.. Also if in case, of balancing across multiple clock domains, that is inter clock domain balancing, sink #s play a important role. When doing a CTS using logic level balancing technique again, the distribution of sink across the design plays an important role.

These reports will help mainly in identifying if CTS is seeing the same number of clock endpoints as designer intends.

Little late though!! My 2 cents :)
 
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