Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

No. of stages in multi-flop synchronizer

Status
Not open for further replies.
T

teja321

Member level 1
Member level 1
Joined
Oct 16, 2006
Messages
37
Helped
6
Reputation
12
Reaction score
1
Trophy points
1,288
Activity points
1,483
multi-flop synchronizer

Hi,

How do we decide the number of stages required for implementing a multi-flop synchronizer.

I know its dependent on MTBF and Process technology. But is there any way we can determine the no. of stages required.

Explanation with the help of an example is most welcome.
 

3 stages synchronizer

No Answers till now...
 

2 stage synchronizer -patent

2 stages is reqired for synchronizer.
once you under metastability, you should understand why you need only 2 stages.
 

number of synchronizer stages

2 stage register is enough for the synchronizer!
 

multiflop

When we talk about a bit synchronizer we never say its a 2-stage synchronizer; we say its a multi-flop synchronizer. It doesn't mean that it has only 2 registers in parallel.

This is an statement from the Atera's paper on metastability in FPGA's.

"To improve metastability MTBF, designers can increase tMET by adding extra register stages to synchronization register chains. The timing slack on each additional register-to-register connection is added to the tMET value. Designers commonly use two registers to synchronize a signal, but Altera recommends using a standard of three registers for better metastability protection. However, adding a register adds an additional latency stage to the synchronization logic, so designers must evaluate whether that is acceptable."

So in this case altera recommends "three" registers. So can we assume that there is a possibility that the second register in the synchronizer stage can also get into a metastable state.

So again my question is "How does one decide the number of synchronizer stages?". What kind of data helps one figure out the number of synchonizer stages required?
 
  • Like
Reactions: ivlsi

    ivlsi

    ivlsi

    Points: 2
    Helpful Answer Positive Rating
synchronizer flop

It depends on YOUR process, flop architecture and the frequency of your data & clocks, like your equation states. If you told us what some of these parameters are we may be able to help.
 
  • Like
Reactions: ivlsi

    ivlsi

    ivlsi

    Points: 2
    Helpful Answer Positive Rating
Atera's paper only covers Altera process and architecture.
2-stage synchronizer is the way to go.
 

Hi,
May be the discussion happened in other thread on the same topic may help. See the answers given.



Thanks,
-Paul
 

    T

    teja321

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top