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DFTC violations ! help me!

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dongdong209

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hi, everyone!
warning:cell s% is unknown(black box) because funcitonnality for output pin s% is bad or incomplete.
warning:cell s% is constant 0 value.
warning:design 's%' comes before design s% in the link library; s% will be ignored.
warning: port s% cannot be used as a scan port. it has been previously inferred as an asynchronous signal.
warning: design 'gvc' contains hign-fanout nets. a fanout number of 1000 will be used for delay calculations involving these nets.

these are the typical warnings. help me !
 

dongdong209 said:
hi, everyone!
warning:cell s% is unknown(black box) because funcitonnality for output pin s% is bad or incomplete.
warning:cell s% is constant 0 value.
warning:design 's%' comes before design s% in the link library; s% will be ignored.
warning: port s% cannot be used as a scan port. it has been previously inferred as an asynchronous signal.
warning: design 'gvc' contains hign-fanout nets. a fanout number of 1000 will be used for delay calculations involving these nets.

these are the typical warnings. help me !
Click to expand...

please refer the user guide, there is detail description in chapter , the block box is your ram module?
 

u can try this
set_scan_configuration -exclude [get_cells YOURRAM]
 
you have lots of problem to know . user guide is best choice for you
 

if you have the bist design around the ram , you don't care the warning of the bbox(make sure all the black boxes are rams.)
 
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