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clock skew is difference of clock signal arrival time between two flops.
If you have two flops which works on the same clock frequency but due to position in the chip they are farther from each other, then there is a possibility is that u will see this problem.
Clock insertion delay is the estimated/realistic delay of reaching clocks from the PAD to each flop after CTS. HOLD violations can be fixed by this.
While doing CTS it inserts Clock buffers before the flops if the clock path delay is more in the second flop, this is actually causing the insertion delay.
insertion delay is the time required for the clock to reach from source to the clock pin of flop.
clock skew is the time difference between the clock reaching to the two different flops.
it may help u.
Hi,
Have you gone through the PT tutorials available in eda board itself? If not then search for it and go through it. That will definetly help you in every manner.
Otherwise the PT manuals also have really very good issues dscussed in proper way.
And if you are more hungry, then better go to solvnet and study there itself by looking into the various issues and solutions.
Note: If you are the beginner then dont jump the stages, follow the way I suggested. You'll get most of it.
Added after 3 minutes:
Here you'll find Resources like PT lab database, Training material, etc.:
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