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Problem with including variables in VHDL for state machines

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uso de variables en vhdl

Ok.. I am a bit confused now.. is this dependent on the tool that is used?

So, what about this situation where a and b are signals in the below code and clkin is a free running clock?

Code: 
process (clkin)
begin
a <= b;
end process;
 

how to declare variables in vhdl

ombadei said:
Ok.. I am a bit confused now.. is this dependent on the tool that is used?

So, what about this situation where a and b are signals in the below code and clkin is a free running clock?

Code: 
process (clkin)
begin
a <= b;
end process;
Click to expand...


The good question that needs to be asked from the very begining is : What do YOU want to do ? .. or What do you want your CODE to do ?

The process that you just coded now is not correct at all. In general, VHDL process is either combinational or sequential .. this is effectively neither (or at least having a coding problem to be comb. or seq.) ..

Let me describe the problem that I see in your code:

1. If you want (a) to take the value of (b) based on clock edge, then you need to have a clock event in your code. The code will be as follows then:
Code: 
process (clkin)
begin
if rising_edge(clkin)
a <= b;
end if;
end process;
In this case, this process will be considered sequential process. And, the sensitivity list should only contain the clock (and the asynchronous reset if available). The synthesis of this circuit will simply be a Flip-Flop that has (b) as input and (a) as output.




2. If you want (a) to immediately get the value of (b) once (b) changes, regardless of the (clkin), then this will be a combinational circuit. And, if this what you want, you should be adding (b) to the sensitivity list of the process (as long as the signals inside the process are not synchronized to a clock edge). If you didn't add (b) to the sensitivity list, you may notice undesired behavior during SIMULATION, but not synthesis.

Code: 
process (clkin,b)
begin
a <= b;
end process;
So, again, what do you want your code to do ?
 

    O

    ombadei

    Points: 2
    Helpful Answer Positive Rating
vhdl declare variable

is this dependent on the tool that is used?
Click to expand...
Supplementing the clear explanation by omara007, I doubt, that it depends on the tools. Using the sensitivity list as shown, you can expect that the code is understood correctly by any tool, either in synthesis or simulation.
 

variables en vhdl

Thanks omara007.. Just wanted to gain a clearer understanding of this process sensitivity list arguments.. I am getting a roughly good idea.. between the difference between simulation and synthesis..
 

sensitivity list falling edge

FvM said:
2. In a process, you can have multiple assignment to a signal, e.g. clkout. While this would be flagged out as a mutiple-source error in combinational code, it's legal in sequential code. Simply, the last assignment wins.
Click to expand...

Just to clarify on the "last assignment wins".. does such a situation arises for signal b when the below code is executed?
Code: 
process (clk,b)
begin
if clk'event and clk = '1' then
b <= b + 1;
if b = 10 then
b <= (others => '0');
end if;
end if;
end process;
 

vhdl + variable + infer

ombadei said:
FvM said:
2. In a process, you can have multiple assignment to a signal, e.g. clkout. While this would be flagged out as a mutiple-source error in combinational code, it's legal in sequential code. Simply, the last assignment wins.
Click to expand...

Just to clarify on the "last assignment wins".. does such a situation arises for signal b when the below code is executed?
Code: 
process (clk,b)
begin
if clk'event and clk = '1' then
b <= b + 1;
if b = 10 then
b <= (others => '0');
end if;
end if;
end process;
Click to expand...

ombadei

In clocked processes, you should not add anything to the sensitivity list except the clock or the asynchronous reset.

If you want the counter to reset when reaches 10, code it like this:

Code: 
if rising_edge(clk) then
 if b <= 10 then
  b <= b+1;
 elsif b = 10 then
  b <= 0;
 end if;
end if;

also, don't mix between using (others => '0') and integer (10). Either you use (10, 0) .. or ("1010", '0').
 

variables is vhdl

Thanks for the invaluable advice. Its been really difficult to learn proper coding, especially since school has never inculcate good coding disciplines.

Well, for now i am doing a video to monitor streaming project, and i have been encountering intermittent and weird results from my debugging. The one problem that arises is when i integrate the modules together and things start to break. So, i am turning to this forum to learn about how things really work.


If you want the counter to reset when reaches 10, code it like this:
Click to expand...
Looks like i have to filter my large code and change the way i do my loop control in my application.:cry:(I have just changed variables to signal integers)

So, in summary, i should always enclose an "if-else" condition checking in such a situation?

Is it because of clarity issues as a programmer or that it will yield unexpected results?


Thanks once again omara007. Your information has been really insightful.
 

vhdl mix variables signals

Supplementing to "the last assignment wins", you have to consider, that all signals are updated after the process is finished. So it's pretty clear, why the above counter example resets in the next cycle after reaching 10 and thus has 11 states (0 to 10).

also, don't mix between using (others => '0') and integer (10). Either you use (10, 0) .. or ("1010", '0').
Click to expand...

I don't completely agree. Provided, the b signal type is unsigned, then you have to use a constant compatible to unsigned in assignments e.g.
Code: 
b <= conv_unsigned (10,4); or
b <= "1010"; or
b <= x"A";
but in a relational expression, you can use an integer constant as well
Code: 
if b = 10 then
I further presume, that there are some places in the code, where integer constants are calculated from parameters, so you're restricted to those constructs, that accept an integer argument. I don't see a purpose in writing verbosely
Code: 
if b = conv_unsigned(10,4) then
if it's not necessary.
 

vhdl variables results

Yes, FvM, you definitly can use whatever representationg/type for your numbers .. Yes, if you declare it to be integer, then don't use (others => '0'). Or, if you declare it to be unsigned, then don't use (10) .. where (10) here means TEN, not TWO.

Still, VHDL does give you the flexibility to do type conversions .. yet, in the given example you don't need to do that.
 

vhdl variable

Code: 
if rising_edge(clk) then
case curState is
.

when st01 =>
nextState <= st02;

when st02 =>
dataOut <= dataIn;  -- Capture Data
 if b <= 10 then
  b <= b+1;
 nextState <= st02;
 elsif b = 10 then
  b <= 0;
 nextState <= st03;
 end if;

when st03 =>
.
end if;

Consider the above loop control with state transitions. Is this a good way to capture my data on every clock cycle?

I am contemplative in placing "dataOut <= dataIn;" after the "if" condition..
 

variables in vhdl

It only captures the input when you transition into state st02.

Move it within the rising-edge IF, but before or after the CASE.

You can also put it in another process separate from everything else, where it's obvious that it's captured on every rising clock edge:
Code: 
U_DATA:
  process (clk)
  begin
    if rising_edge(clk) then
      dataOut <= dataIn;
    end if;
  end process;
 

when to use vhdl variables

when st02 =>
dataOut <= dataIn; -- Capture Data
if b <= 10 then
b <= b+1;
nextState <= st02;
elsif b = 10 then
b <= 0;
nextState <= st03;
end if;
Click to expand...
The elsif condition is never true and the state machine caught in st02.

P.S.: Because the b = 10 reset condition doesn't work, a 32-bit counter is implemented from the integer signal b, unless a range has been specified. To my opinion, integer signals are preferable for internal counters and similar purposes, but they should have a range to clarify the intended bit width.
 

Re: Variables in VHDL

FvM said:
The elsif condition is never true and the state machine caught in st02.
Click to expand...

Do correct me if i am wrong.

For a signal std_logic_vector, it will get caught in st02?
For a signal integer, it doesn't get caught in st02?

Added after 24 minutes:

Just another question on top of state transition control.

In a state transition where it is clocked, is there a threshold with nested-ifs checking?

For eg.
Code: 
if rising_edge(clk)
case curstate is
when st0 => nextst <= st1;

when st1 =>
 if a = '1' then
 nextst <= st1;
 else
  if b = '1' then
   nextst <= st2;
  else
   nextst <= st3;
  end if;
 end if;

when st2 => ..
when st3 => ..
end if;

I hope i am not being to bugsome. Please pardon me for my incessant questions on the basics. For my project, i have worked out my logic and simulation looks fine but when implementation comes in play, things just crash.
 

Re: Variables in VHDL

For a signal std_logic_vector, it will get caught in st02?
For a signal integer, it doesn't get caught in st02?
Click to expand...
The syntax isn't valid for std_logic_vector. The problem is, that b<=10 includes b=10, so the second condition isn't evaluated at all.

I don't understand, what you mean with a threshold in this case. All if levels are evaluated, generally. There's no limit for their complexity.
 

Re: Variables in VHDL

The syntax isn't valid for std_logic_vector.
Click to expand...

Thanks. That means there's still a fundamental difference between signal integers and signal std_logic_vector. Well, i always thought that there is no difference as they belong to the signal type.

I don't understand, what you mean with a threshold in this case. All if levels are evaluated, generally. There's no limit for their complexity.
Click to expand...

The if-else structure denotes comparators. So, i was just wondering that if we have nested if-else (shown in the above code), do i have a sense of control in how my state machine behaves.
 

Re: Variables in VHDL

do i have a sense of control in how my state machine behaves.
Click to expand...
The behaviour is completely deterministic. I don't see anything unclear with the nested if statements. They are evaluated left to right.

That means there's still a fundamental difference between signal integers and signal std_logic_vector.
Click to expand...
There is a difference, that integer hasn't a defined bit width. But I in the example, I simply refered to different syntax for numeric constants. That's not fundamental, but a difference.
 

Re: Variables in VHDL

Hi again,

I need to resolve the below three equations. I understand that there are some complications in using the 'numeric' versus 'arith' packages.

Can someone advise on how should i approach it?

Y, Cr, Cb are std_logic vector as inputs. (8 bits each)
I need R, G, B as std_logic_vector outputs. (8 bits each)

R = Y + 1.371(Cr - 128)
G = Y - 0.698(Cr - 128) - 0.336(Cb - 128)
B = Y + 1.732(Cb - 128)

There are overflow cases i need to catch and clamp it at the minimum or maximum values(since its fixed width). I removed the floating points by multiplying throughout by 128 and there will be a fixed constant coefficient. From what i understand, if i can convert the values as integers, life would be simple but i am taking the pessimistic side of things for now.
 

Re: Variables in VHDL

I understand that there are some complications in using the 'numeric' versus 'arith' packages.
Click to expand...
There are different opinions about better using legacy std_logic_arith or more recent numeric_std libraries. Basically, both are working. If you are starting a new project and don't have to deal with old libraries, you should go for numeric_std.

Your problem can be perfectly handled by the new VHDL fixed point packages. They provide a fractional number representation as well as saturation logic. See http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/index.html
Of course, these operation can be also performed with a standard arithmetic library manually in your code.
 

Re: Variables in VHDL

Before exploring that option, wouldn't floating point arithmetic be more time consuming in hardware representation? Then, what would the synthesis be like?
 

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