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Clock Gating VS Area question

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Zorbas-E-

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why clock gating using muxes

Hello all!

I'd like to ask you if you have noticed the same as I did when inserting clock gating in a design. I use Synopsys tools, i.e. Design Compiler-PowerCompiler for that.

So, what I observed is that when I apply clock gating the circuit area shrinks!
A little (1-2%), but is gets smaller.

Why does this happen? I mean, wouldnt you expect to grow a little by the introduction of the extra clock gating integrated cells?

thx for your time and reply in advance!
 

clock gating + area saving

The area shrinks becauses the multiplexers that are used to allow a FF to retain it's value are no longer needed as when the clock is gated the FF retains its value.
 

    Zorbas-E-

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insert clock gating

Yes!

That's a very good explanation! I was just checking powercompiler manuals now and was thinking that this could be the reason after seeing some nice pictures it has in there.

Now I have another question which bothers me.

When I do power driven clock gating with saif annotation the tool decides to gate for example 60% of my registers. When I disable it and go the typical way then the tool gates 91% of the registers, thus improving dynamic power by 10% and also area!

Why does this happen, power driven CG algorithm is supposed to be much better!
 

what does doing the dynamic clock gating

Are you using the same switching activity for power analysis as for optimisation?
 

Yes, the flow I'm following is as follows:

After elaboration (GTECH) I insert clock gating and compile once. No saif annotation here.

Then after i get the first clock gated netlist, I simulate it and get a saif file out of the simulator. Then I go back to the synthesis flow, enable power driven clock gating and read in the saif annotation. Then I incrementally compile once again for power driven gate level clock gating.

Then after I get the final netlist, i simulate it again and then do power analysis.

So, my results with power driven are worse compared to still doing 2 compilations for optimization but with power driven CG disabled and no saif involved.

Am i doing something wrong?

Thanx for your consideration!
 

Please I would like to have some opinions!

I think that the power driven algorithm doesnt take into account the muxes that ar gonna left behind if it decides not to clock gate some registers. So in the end that's why I get more area and more dynamic power.

Is it that the algorithm is not efficient?
 

crosscheck saif annotation, as that should give better dynamic power than typical one.
 

Yes this is what I'm doing, please read previous posts. Before enabling power-driven clock gating I simulate and fetch SAIF annotation of the netlist to be clock gated. Therefore the tool knows which registers are busy and which arent't.

The thing is that it decides to go only for 60% of the registers thus leaving lots of multiplexers untouched. This results in larger area and power dissipation in comparison to what I get when I do typical clock gating and the tool just clock gates almost all registers (92%).

There has to be something wrong with the algorithm. Whats your opinion?
 

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