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Yes. But the design tools may issue warnings depending on the settings. Latches have to be implemented as combinational loop with most programmable logic devices, so they can't be avoided in some cases.
Hi,
Combo-loop backs are sometime un-avoidable and it is permissible in case-by-case due to design requirements and performance issues. Some of the tools will give warnings and some might not give any warnings at all for the Combo-loopbacks. While doing GLS, these combo-loopback scenarios are very oftenly seen while the back-trace.
Eg: Some State Machine designs you cant avoid the Combo-loopback, still that case-by-case.
Thanks Paulki!
can you please elaborate it.it would be great if u can give Example.
I recently took a interview and i answered the same as you have written above but he was saying DAT CFL should not be present in design even in state machines also..
Hi vikas,
Its true to avoid the Combo-Loop back in the design. But I've seen in a very popular processor IP, multiple places combo-loop presence (especially in the Pipe-line stages and some State Machine). Example right now I dont have and from the DFT team members they said its difficult to stitch the SCAN in Combo-loop path. The explanation is DFT people has to break combo-path with some tie LOW/HIGH logic without affecting its Functionality. If m missing or giving wrong info on the DFT, any DFT experts can correct me.
The most serious problem with combinational loops is to guarantee, that their input signals are glitch-free. As an example, the enable signal of a latch must not have glitches from inactive to active state, otherwise a wrong state would be latched. But when the said enable signal is an output of combinational logic, it can't be guaranteed to be glitch-free in any case.
Paul, processors probably have one of the most stringent timing budgets, but that would be an exception rather than a rule. Another interesting observation I have seen previously is simulator going in infinite loop (time not moving) due to combo loopback in the designs. Basically the update value of a logic used to feedback the logic itself. Due to this, the new update is scheduled in next delta and this continues forever
Hi Sharan,
What you said is extremely true with the Combo-loopbacks in the simulation perspective (Infinite loop).
As FvM said, for Combo circuits, input should be glitch free otherwise un-expected results may come. What I said is not a "rule", but while optimizing design by the synthesizer "or" some designers are stick on their designs with Combo-loopback, In these cases a verification/DFT guy has to do their on alternative without affecting the functionality. Ideally speaking most of the designers will not prefer combo-loops in their design, the major draw-back of such designs are most susceptible to the DEAD_LOCK.BETTER AVOID COMBO-LOOPBACK IN DESIGNS.
Hello Paul,
On what cases we HAVE TO use combo loop? verification has problem of infinite loop with combo loops, synthesis tool may give warning about combo loops, DFT guy requires to break it to achieve expected coverage & actual ASIC may have glitches when combo loop i used.. than what is it that is making designers use combo loops ?? Are there ANY advantages ??
Hi Jaydip,
Apart from "Timing" I dont know anymore advantages for the Combo-Loopbacks. Im not that much experienced to comment on why some designers are not ready to re-design their combo-loop designs. Have seen sometimes some of the Synthesizer tools are wrongly optimizing the design with combo-loops. Usually those cases will be eliminated during the next round of synthesis with proper constraining.
Hi Vikas,
Ofcourse the combo-loopback will create problem in "Timing". What we are trying to achieve that itself create problems here..... example is already discussed like "Infiite loop".
Jaydeep, when Paul says timing advantage, he means that at places combo feedback is used to avoid having to wait for 1 cycle to take a decision. At such places, you put feedback to get 1 cycle timing advantage. I am not able to recall an example, but vaguely remember that in processors if w/o combo loopback the pipeline would stall for a cycle. Probably in the next pc value computation where after next pc address is computed it should be compared for cache match and read out all in one cycle. But I am not very sure ...
Thanks All,
On the basis of our discussion I would say that we should not use CFL until it is not required in our design..
Thanks to you all to participate in the discussion and help me in growing my knowledge.
to be continued: when you specify CTS spec in your backend tool(such as encounter), you will get some information that CTS detects loop in clock XXX and set ExcludedPin at term XXX. what is the impact on the design?
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