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FPGA implementation-fft implementation using cordic algoritm

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nagu guptha

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FPGA implementation

I am doing my project on fft implementation using cordic algorithm......when we put it for synthesies its taking 12-15 hours to complete.......so pls tell me wats the problem......the problem will be with our code or something else........
 

FPGA implementation

Which tool are you using. I am assuming you are using Xilinx ISE suite. If you have synplify pro, you can do a quick check to see if your code is the problem. Else try to reduce bit lengths of your variables and synthesize each module independently.
 
Re: FPGA implementation

Hi,

also check support for your synthesis tool as if you are using Symplify then it is not supporting two dimensional arrays (Verilog). And yet you will try it took too much long time to synthesize it. This is just an example. Another thing you can do is add constraint like False path etc this way it will be faster.

HTH
 

Re: FPGA implementation

thank u very much.....the guidance which u gave really helped us a lot to debug our errors......
 

Re: FPGA implementation-fft implementation using cordic algo

hi...have you completed your project? if so, can u help me in my project too. i'm in need of distributed arithmetic based fft. can anyone help
 

@nagu.. i m new here and doing almost the same project, can you help me?
 

hey can i get the design diagram of implementation of FFT using CORDIC algorithm?
 

i am unable to incorporate cordic into FFt vhdl code
how to run open core projects using Xilinx 14.7 please help me
 

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