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how to make pullup time and pulldown time equal ?

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sevid

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pull up time

hi,everyone

how to make ur pullup time and pulldown time equal in ur gate, for example, a 4-input NAND gate.

if the efficient resistance of a NMOS in the pulldown network is Rn, the total resistance is 4Rn.

but what's the total resistance or average total resistance of the pullup network, if one PMOS efficient resistance is Rp.

probability is used here?

thanks

sevid
 

pull down pull up network

There are two aspects. One is theoretical aspect. For this you should consult CMOS VLSI design book by David Harris. For PMOS, it is Rp and Rp = 2*RN. But PMOSes are in parallel and you have to take it like a resistor network where PMOSes are in parallel.So that makes Rp = Rn/2 since 4 PMOSES are in parallel. In series there are 4 NMOSES and their effective resistance is 4*RN. Now to make it equal to effective RP = Rn/2, they need to sized up by a factor of 8 i.e., Rn/8 + Rn/8 + Rn/8 + Rn/8 = Rn/2. This is one choice of sizing.

If you are doing HSPICE simulation, these theoretical numbers are not accurate and you have to manually do hit and trial until you get equal rise and fall times.

Hope this helps
 

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    sevid

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html + dependent pulldown

hi, tariq786, thanks a lot.

but for the first method, the input will be 0000 or 0111, and the efficient resistance is not equal obviously.

i.e., one, two, three, or four PMOSes of the pullup network will be on for various inputs.
does probability need to be taken into account here ?

sevid
 

calculate rise time pullup

it can be obtained from the worst case and best case, rather than the probabilities of the inputs, i think.
 

equal rise and fall time

Considering the Nand4 gate:

1) The pull up time will be data dependent, i.e. you have to see how many PMOS are ON at a time. Worst case will be 0111 and best will be 0000
2) For pull down time, due to velocity saturation, the effective resistance of the Four series NMOS will be reduced, so you will not see a 4Rn but less may be 2.5Rn to 3Rn.
 

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    sevid

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equal rise and fall time nand

hi, everyone

"2). For pull down time, due to velocity saturation, the effective resistance of the Four series NMOS will be reduced, so you will not see a 4Rn but less may be 2.5Rn to 3Rn. "

can u explain it clearly ?

plz
and
thanks

sevid
 

equal pullup and pulldown

If transistors are in series, the effective Vds seen by each transistor will be less and hence they will have less velocity saturation and hence more current and hence resistance decreases.
 

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    sevid

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nand gate equal rise time and fall time

hi, animeshjn
thanks for ur help
sevid
 

why do we need equal rise and fall time

Hi,
One more solution is:

Use the spice level netlist of the 4 i/p nand gate. Once you freeze on the rise time or fall time.. make the width of the PMOS or NMOS as a variable and sweep it in your spice simulation to match the risetime/falltime...

Hope this helps.. if not ping bak.
 

pull-down time

Why we are checking best case and worst case in the case of PMOS only why not NMOS..............
 

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