eda_wiz
Advanced Member level 2
ams 0.35
Hi folks,
am designing a digital chip in AMS .35u library. Inorder to reduce power I would like to used a scaled Vdd of 1.2 V instead of the 3.3V (nominal) specified by the vendor.
The has been simulated correctly in Nanosim with the scaled Vdd. However I am unsure whether DRC (esp transition)will be satisified. Pleas give ur comments.
have anyone used lower Vdd(than specified) for digital design , please help..
tnx
eda_wiz
Hi folks,
am designing a digital chip in AMS .35u library. Inorder to reduce power I would like to used a scaled Vdd of 1.2 V instead of the 3.3V (nominal) specified by the vendor.
The has been simulated correctly in Nanosim with the scaled Vdd. However I am unsure whether DRC (esp transition)will be satisified. Pleas give ur comments.
have anyone used lower Vdd(than specified) for digital design , please help..
tnx
eda_wiz