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Output Delay Problem For 32 bit output (+ 50 points for sol)

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khamitkar.ravikant

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xilinx behavioral register output grounded io

Dear all
i m taking the output from cryptographic system in 32 bit fromat and at the end by using 32 bit register i m taking output.
but problem is that the clock at each flip-flop of register reaches in different time that is skew problem due to delay and the output varies for 1.5ns approximately and then stablize. so what i can do to avoid such a behaviour in
my system so i can get the output stable .
as attached waveform shows output varies according to the clock
so please do somebody help me out.
 

output delay

khamitkar.ravikant said:
/.../problem is that the clock at each flip-flop of register
reaches in different time that is skew problem due to delay and
the output varies for 1.5ns approximately/.../
Click to expand...
the problem [I guess] is not in the clock skew but in output
registers placement, the delays from F-F outputs to pins
vary from register to register;
you can:
- force ise to put the registers in I/O cells;
- specify a constraint: 'clock to output delay' to
a low value, let's say 0.6ns what makes the placer
to put the F-F's close to I/O's;
- place to end F-F's manually near to I/O's [floorplan];

the first option seems to me the best;
I don't know to do it in xilinx tool, this you have to
find out yourself, good luck ...
---
 
iodelay spartan 3

thanks for reply as i m working on this problem i m sure i will get solution and u r help too is also worth so will relpy as soon as got solution ok
.
 

vhdl code for32 bit processor

what you can do is to add final stage of D flip-flops, to make the registration of the output signals. that way you will get all your elements synchronized.

no need to force yourse ISE or anything... just add them in VHDL code of your design.

you can use the generate statement and instantiate 32 FDR flip-flops, or you can construct your own D flip-flop and make it to have some width of signal...say 32.. then instantiate those flip-flops at the final stage of your design before sending those signals out of the chip..

here is a code for customizable flip-flop
Code: 
entity dff is
   generic(
   width : integer :=32
   );
   port( clock:   in std_logic;                  
         ckena:   in std_logic;                     
         reset:   in std_logic;                      
         d:       in std_logic_vector(0 to width-1);     
         q:       out std_logic_vector(0 to width-1);  
end dff;

architecture behavior of dffn is
   begin
      process(clock,reset)
	     begin
            if(reset='1') then
               q <= (others => '0');
            clock'event and clock = '1'
               if(ckena='1') then
                  q <= d;
               end if;
 	        end if;
      end process;
end behavior;
 
xilinx & output delay

What do you plan to do with the design ? .. Have you tried downloading the program onto the board and checking for operation ? ...

Try using the gloal resources ....the low skew lines !!!
 

xilinx spartan-3e delay output clock

ok
 

what is output delay

there is significant improvement in the results as i placed the ctout in IOB part and uesd PACE tools to place the same.
results are improved from 1.8ns to 1.0ns that is improvement of 800ps. and the device i am using this time is spartan 3e 1600 fg320-4 so if possible let me know further how can i improve the performance of output.
 

spartan3 offset constraint iodelay

trying placing a "OFFSET OUT AFTER" constraint on the bus
 
xilinx iodelay ucf

setting the timing constraints as mentioned before, a normal thing to do. with xilinx it is done in the UCF file. If you dont know how to do it, check an appnote: https://www.xilinx.com/support/documentation/white_papers/wp331.pdf or https://www.seas.upenn.edu/~milom/cse372-Spring06/xilinx/cgd.pdf

How did you assign the pins to the FPGA? based on board routing? I am not shure how to check it, but probably on the silicon the pads (chip-to-package balls) are in a single line (like in a QFT package), but then the BGA package internal routing mixes them up. So, if its possible, you could make shure that your D-flipflops of the IO register are in one line and next to each other, so assigned to pins having their die-pins in one-line. this can be changed by pin assigment. so first assign signals to IOBs, then they will determine the pins to use.
 
using 2 32 bit register make output of 8 bit

did these help? and how much? please inform us.
 

Re: Output Delay Problem For 32 bit output (+ 50 points for

What device are you using? I'm assuming it's a Xilinx part. The Virtex 5 parts (maybe others?) have an IODELAY primitive which lets you add small delays (tens of picoseconds) to the output. This is a great way to deal with differing PCB trace delays.
 

Re: Output Delay Problem For 32 bit output (+ 50 points for

As you are targetting a Spartan3E device. Why don't you use the floorplanning included in ISE?

The encrypted block can be placed near the outputs, use constraints manager to minimize pin to pin delay and clock to out delay.

If you don't know how to achieve this, read the manual on design planning, floorplanning and contraints

I'm sure you'll find what you need.
 
Re: Output Delay Problem For 32 bit output (+ 50 points for

take care, about grounding ur circuit, please ensure that ground signal is 0 v( usually using wide cable/ wide area), and the second is take capacitor 100nF to power supply(+ -)and dont forget use stabilized power supply with 7805
 

Clock all output signals, Using the registers in IOBs
 

i am very happy to tell that i completed all the implementation of the system like
i am giving input from gui designed inside VB on PC
and kit gives results of encryption and decryption and they get displayed back.
also edk tools are used and microblaze core is used to implement the design also AES as core is attached to microblaze and hardware accl. is achieved.
thanks and regards.
 

Re: Output Delay Problem For 32 bit output (+ 50 points for

Hi khamitkar.ravikant,

can you tell me what was problem for you and what was solution?

--
Shitansh Vaghela
 

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