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any provision of signal attributes in verilog ?

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nagu guptha

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verilog...

Do we have any provision of signal attributes in verilog, like 'event in vhdl.
Is it possible to check positive edge of clock in behavioural statements like TASK and conditional IF statements.
please do reply.....
 

verilog...

'event is similar to @ in Verilog.

@(posedge signal);

Will wait for a postive edge on signal. This can be used in tasks.
 

Re: verilog...

Thank you for replying......,it was a useful information.
 

verilog...

that is right!
 
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