Questions about using CeltIC tool

Hello All!
I'm using Cadence CeltIC tool at the first time, so I have some (maybe stupid) questions. Could you please help me and answer them. Unfortunately I couldn't find anyone who can help me at my work Thanks in advance!

1) First of all I have to make noise library (.cdB) using make_cdb utility. But I cannot really understand what netlist should I use as input for this tool? Should I use SPICE netlist without or with parasitic element? Or maybe I should use dspf file?
I tried different variants and every time make_cdb utility gave me different results.

2) After completing cdB library I run CeltIC. What kind of analysis can I do? Only glitch noise analysis or maybe noise-on-delay analysis too?
Unfortunately I don't have PrimeTime, so is there any other way to get twf file?
Thanks again!

.cdb noise library

Could anyone please help me? The time is going out...

how to make celtic cdb

I'm not sure the exact inputs to create cdBs (i have only used, not created), but I will try to explain them to be sure you are using them properly.

When running Celtic at the top level of your design, cdBs are used for any parts of the design where you are pulling in .lib/lef files. This can be std_cells, memories, or hard-blocks. You do not need to create a cdB for the top level of the design for doing analysis at that level. Only if your block will be used as a hard-block of a larger design will you need to create a cdB. Then, whoever is using your hard-block (pulling in .lib/lef) will also need to pull in the cdB. Hope that makes sense.

Celtic standalone can only do glitch analysis. You need Celtic plus a timing tool (pt, cte, ets ...) to fully perform noise-on-delay analysis. If you have encounter, you can call Celtic from your timing run with timeDesign -si. If not, Celtic can create an "incremental sdf" file which you then load into you STA tool. Your normal STA runs will now have noise-on-delay information when doing timing analysis. Celtic does not need a twf file to create the sdf, it will use infinite timing windows instead (but this will be more pessimistic).

what is cdb in noise analysis

pavelni said:

Hello All!
I'm using Cadence CeltIC tool at the first time, so I have some (maybe stupid) questions. Could you please help me and answer them. Unfortunately I couldn't find anyone who can help me at my work Thanks in advance!

1) First of all I have to make noise library (.cdB) using make_cdb utility. But I cannot really understand what netlist should I use as input for this tool? Should I use SPICE netlist without or with parasitic element? Or maybe I should use dspf file?
I tried different variants and every time make_cdb utility gave me different results.

2) After completing cdB library I run CeltIC. What kind of analysis can I do? Only glitch noise analysis or maybe noise-on-delay analysis too?
Unfortunately I don't have PrimeTime, so is there any other way to get twf file?
Thanks again!

Click to expand...

My two cents...

As a circuit designer, i only have transistors as the basic elements. When i build gates, i use spice models to see the behaviour of the transistors(spice models correctly model the behaviour of the mosfets).

But when someone takes your designed gates, he needs to know the full detailed behaviour of those gates. Thats the reason why you give timing(.lib), noise (.cdb) and other views. Its something like you are going one level up the hierarchy from transistors to gates. I hope this makes sense.

For your second question, i agree with shelby. You need an STA tool to do the correct timing analysis. Normally, designers prefer generating the incremental sdf and subsequently feeding it to STA tool. To get a realistic picture, give a timing window where you expect the activity to happen/take place in your block else your timing analysis will be slightly pessimistic.

regards.

can celtic take timing windows from pt

Thanks a lot for your answers!
But I've got another question
Our company makes memory (RAM) and so we give different views of our memory to the customers. One of this view - is .cdB. The next files are the input for make_cdb utility to create .cdb view:
.lib file and dspf file from RC extraction.
If I understood you correctly we should use ideal hierarchical netlist of our memory to create .cdB view of the toplevel?
But now we use parasitic netlist for cdb creation. Is it mistake?
Thx in advance!

celtic timing lib

pavelni said:

Thanks a lot for your answers!
But I've got another question
Our company makes memory (RAM) and so we give different views of our memory to the customers. One of this view - is .cdB. The next files are the input for make_cdb utility to create .cdb view:
.lib file and dspf file from RC extraction.
If I understood you correctly we should use ideal hierarchical netlist of our memory to create .cdB view of the toplevel?
But now we use parasitic netlist for cdb creation. Is it mistake?
Thx in advance!

Click to expand...

Transistor -> Gate -> Logic Block.

By hierarchy, i mean one level up the design from transistors to Gates.

For a circuit designer, the basic element is a transitor but a PnR designer will have a gate as the basic element. He should not be worried about the transistors inside the gate as long as a circuit designer gives him a true picture of the circuit in the form of .cdb files. Since a circuit designer does not do PnR stuff and a PnR guy does not bother about transistors, its important to do a proper handshake between the two (unless the memory in question a custom memory.

Parasitic netlist will give you a true picture of how noise is propagated in your design. Just look inside the dspf.

I am not sure if i understood your question corrrectly. Did i answer your question? Feel free to ask.

encounter dspf

onlymusic16 said:

pavelni said:

I am not sure if i understood your question corrrectly. Did i answer your question? Feel free to ask.

Click to expand...

Yes, thanks a lot. You have answered my previous question!
And another one is:
I've got RAM that consists of many blocks. I also have .lib file for the whole memory and dspf file from Calibre extractor that contains Instance (transistor) section for the whole RAM and Net (parasitics) section.
I've also got an opportunity to create parasitic netlist in spef and spice formats.
So if i have this files may i use CeltIC to analyze noise glitch propagation inside my RAM?

Click to expand...

celtic cdb

I guess my question is not understandable.
I'll try to explain:
I want to use CeltIC to check my circuit for glitch noise or crosstalk violations on the gate level. Is it possible?
And if not - what tool can I use to do this, i.e. to operate on the gate level of my circuit?
I hope this is more clearly...:|

celtic make_cdb ram

pavelni said:

I guess my question is not understandable.
I'll try to explain:
I want to use CeltIC to check my circuit for glitch noise or crosstalk violations on the gate level. Is it possible?
And if not - what tool can I use to do this, i.e. to operate on the gate level of my circuit?
I hope this is more clearly...:|

Click to expand...

Yes, its possible. Celtic NDC Si aware delay calculator can do that stuff. I am putting up a small doc which shows the flow. You can go through the detailed documentation available on sourcelink.

Feel free to ask for any doubts.

best regards.

make_cdb

And what's the difference between celtic_ndc and celtic itself?