dithering in sigma delta

dithering sigma delta

what is dithering and how is it used in delta sigma modulator. how does it help in improving the noise performance. thanks in advance.

sigma delta dithering

Dithering in SD modulators is to slighty vary the input signal randomly at every sampling instant. In a SD modulator or any other data converter for that matter the noise floor(assuming no other non-idealities like thermal noise, non-linearities etc) is determined by the quantisation noise(which depends on the resolution of the converter). When doing linear analysis it is assumed the quantisation noise is purely random(white noise) that is spread across the entire frequency spectrum(depends on the sampling frequency).

Now to get that kind of quantisation noise the input signal should cover the entire range of the converter(all the values), which, often, is not the case in real applications. Suppose if you apply a DC voltage to a SD modulator without any dithering(randomisation) then you'll notice that there are spurious tones(spikes at certain frequencies) which rises the noise floor thereby decreasing SNR.

You can dither your input simlpy by dynamic element matching or other techniques.

dither delta sigma

thanks for your reply kishore2k4, it helped me.

how is that dithering done in practice, you specified dynamic element matching and other techniques like, can i know what is dynamic element matching and if any other techniques too.

sigma delta dither

This is important and urgent please respond.....

digital dithering circuit

No one knows it?:|

dither sigma delta

Someone please recommend a book on this subject.
I recently saw an implementation of a sigma delta fractional PLL with good phase noise performance and wonder how that was achieved.

sigma delta dithering

Dithering circuit is typically implemented as input sampling
circuit, but which is sampling reference voltage with small scale factor (say 1/20 of full scale coefficient) and with periodically alternating sign (at frequency which will be rejected by digital postfilter).

dithering, dynamic element matching

Still not fully understand.Could you descride it more detail or some material recommended ?

Thanks

mikersia said:

Dithering circuit is typically implemented as input sampling
circuit, but which is sampling reference voltage with small scale factor (say 1/20 of full scale coefficient) and with periodically alternating sign (at frequency which will be rejected by digital postfilter).

Click to expand...

There are a lot of articles dealing with dithering. Please see attached paper from very fast search.

Thanks for sharing!