Verilog Newbie Question: Please Help

Can someone tell me why this only shifts once and not every clock edge?

Try this should work

input [3:0] d;
input clk, rst;

output [3:0] q;

reg [3:0] hold;

always @(posedge clk or posedge rst)
begin
if (rst)
hold <= 0;
else
hold <= d >> 1;
end
end

assign q = hold;

asic-Ganesh you are wrong and don't understand blocking and nonblocking. Non-blocking evaluates the right hand side of all nonblocking expressions First and then assigns to the left side variable. Think about his code:

hold <= d >>1;

every clock edge d is fixed. This means that every clock cycle the original value of d will get shifted once and then assigned. If d doesnt change it will be the equivalent of doing only one shift on the same piece of data over and over again. If you want to shift out the contents of d you need to do this:


The above code will convert the parallel data in d to serial data in q. Hold is being updated with every shift operation. The process will stop when all the data has been shifted out of hold and hold is reduced to 0. Read up on non-blocking and blocking statements. Its tricky to understand at first but this is a good example illustrating the importance of the subject. Good Luck!

there is no point of blocking and non blocking assignments w.r.t the question asked by digital-newbie.

If he wants to have shift in every clock cycle, input d shoulb be toggling in every clcok cycle. Check the input "d", if u give 4'b1111 as input and at everyu clock edge u will see the o/p signal high all the time

Thanks for the responses. I don't think I phrased my question correctly. I wanted to shift out all the bits of the input into q. So basically a parallel to serial type application. L0gik's solution was the work around. Thanks for the help!