Help Needed:Class 0 ESD safe wirebonding:Bond sequence,tips

can you bond to the esd mat

Hello everybody,

I have a 130nm CMOS IC that has no ESD protection, and I am in the phase of making the test PCB for it. The chip is not packaged, it is a bare die. So, it will be wirebonded on the pcb (using a K&S4522 manual wirebonder).

An ic at 130nm and with no esd protection needs to be processed in a class 0 esd assembly environment (that is HBM<250Volts), otherwise it will probably be damaged.

I am wondering if there are any measures to take in order to increase the yield.

A list follows including what I have come to so far:

1.Regarding the Human body model -> use of esd safe table mat, esd wrist straps, or even esd floor
2.Regarding the charged device model --> the chip will be unpackaged only in the esd protected area (that is on the esd table mat, by an operator with wrist strap). Also any insulator (which can hold charge) will be in a safe distance
3.Regarding the Machine Model -> I have concluded that it is better to have already soldered all the other components, and leave the wirebonding of the IC at the end. I don't know however if the head of the wirebonder gets charged electrostaticly, at which rates and what voltages to expect...Before the wirebonder, there is also the die bonder in action.
I believe that a wise wirebonding sequence would be like this:
gnd
IO
gnd
IO
...
That is, the first pad to bond probably has to be a ground (unless there is a gate directly connected to gnd). This first bonding will probably (I hope) not hurt the IC (At this time there will only be a connection of the IC and the PCB via the adhesive - should the adhesive be electrically conductive or nor?) What is more, if the wirebonder head had some electrostatic voltage, it will probably be discharged.. So, the next bonding could be to a more sensitive IO pad.
If there is a process that accumulates charge in the wirebonder head, maybe after some time the voltage of the head is increased again. That's why I propose to bond successively one gnd after one IO pad, so that any accumulated charge gets away.

Another idea, especially useful for the first bonding could be to inverse the loop of the wire bonding. What I mean is, first touch the PCB, so that the voltages of pcb and wirebonder head equalize, and then the ic.

Maybe, the pcb can include shorts in a clever way, so that esd events take a more controlled current path.

Anyway, these are just thoughts, which I cannot evaluate...

So, if anyone has experience in wirebonding very sensitive ICs, I would appreciate if they could comment on my thoughts, if there is any reasoning behind them. Or, preferably, provide some tips that are known to have good results

Any answer is welcome!
Thank you very much in advance,
mixaloybas

hbm class 0 components

Hello mixaloybas,
You will have to forgive me for being a little harsh but some of your understanding regarding ESD and handling are very naive and incorrect. Its not personal, I just want you to clear your mind a little and take a different approach to your mode of thinking.

I will start with this...the different ESD standards, such as HBM, MM, CDM are not true or exact representatives of ESD events, rather they model characteristics found in the infinite variety of ESD events, and each one attempts to model a certain variety of ESD events based on a simplified classification of ESD events.

Trying to solve HBM, by for instance using esd straps and mats is not a correct approach. When it comes to creating an ESD safe work environment...it is not from an approach of HBM, then CDM than MM...it is more or less a global "lets minimize all voltage fields in the area and potential current spikes". So my first advice is do not approach the design of an ESD work area by attempting to target the ESD standards...it doesn't work like that.

For your work area I would recommend referencing works such as this:
**broken link removed**

and taking a short course such as this:
**broken link removed**

Here is a very good compilations of training materials for ESD compliance:
http://www.automatedlearning.com/products/class_0_esd_article_links.cfm

There is a lot to consider in an ESD safe environment...one, of many examples, is ANY electronic equipment nearby can create problems...transformers, inductors, flowing current, power cables can all setup magnetic fields that can induce charge in parts sitting in a tray on your ESD work bench...you need to know how to look for problems such as that, these courses and information can teach you.

Now on to your wirebonding concerns...my first comment is that when handling your die, the first and primary events it will experience immediately prior to wire bonding is handling...the moment the die is removed from the package, it experiences an ESD event...it again experiences an event when placed on your PCB for wirebonding..you can't wirebond the die unless it is die attached to your PCB..usually through a ground plane-die flag. Unless your die is SOI, it will immediately discharge its entire substrate to the pcb when placed. As long as the bonder is at the same potential as the PCB, your bonding order beyond that does not matter. If however you are working with an exotic cmos chip, with fully isolated SOI, or so forth, the die attach will not immediate equalize the field between die and pcb..in which case your fist bondwire should be the largest on-chip ground...after that the rest of the die is at the same potential as the pcb.

Wirebonding is not your ESD risk...handling the part immediately prior to wirebonding is. My first recommendations is to ensure that your die are in ESD safe waffle packs...your handlers can have no major electrical components near the die that will potentially expose them to fields. Ground everything to die container first before picking a die...make sure the rest of the environment adheres to class 0 ESD standards as will be mentioned in some of the materials I posted links to. There is really so much more to consider that I feel even this last paragraph is incorrect as even a starting point. I can not do it justice in a message forum like this.

Good Luck!
-Srftech

wire bonding esd mat

Hello Srftech,
No prob about your "harshness"
I got your point and you are absolutely right.
Actually, after my post (and some helpful PMs) I had much more studying on this (I found Al Wallash's material very helpful), and it turned out that I was missing the big picture...

I am very interested in the first link you provided,
**broken link removed**
but unfortunately it generates a "Session Cookie Error".
Can you please provide the keywords that led you to this link?Or if you know the title of this work?Or the pdf?
It would probably be useful for others that also watch this topic.

My conclusions up to now:
1.This task is feasible; guys from the (probably more sensitive) GMR disk drive heads industry can do it with success
2.A special esd control program is required. However, the problem here is that as far as I know, the place where I will do the bonding has no esd control program (not to mention about class 0). So i see two choices: Either persuade them to follow an esd control program,which means cost for them..., or try to find class 0 certified microelectronics packaging company (i am sure there's not one in Greece..). I suppose there is a way to check if a company is class 0 certified..


>>Good Luck!
>>-Srftech
I will really need it!

Thank you very much for your recommendations
mixaloybas

esd wire bonding

Sorry for the delay mixaloybas,
I have been traveling lately and I do not tend to check the the chat boards when I travel.
So to answer your questions:

Work area: here is a better tutorial:
www.minicircuits.com/pages/pdfs/an40005.pdf

For other links, you will want to search terms such as esd, control, workarea...etc.

With regard to your packaging house. I can not imagine they have no esd controls? That would risk every product they packaged period...and in truth it would be in their best interest to implement some form of basic controls wether it be simply mats, straps and air ionizers.

If you do not need huge numbers of parts, it may be in your best interest simply to attend the bonding process and ensure they handle everything with utmost care...ensure yourself that you have the right package containers, portable straps, whatever you can to carefully handle the chips. You may lose a few, but you should be able to get several others assembled and shipped back to your lab.

If we are talking mass production, don't both unless you can tolerate significant losses due to esd failure.

These comments are by no means complete, but they should be a good starting point.

A little late but I still hope it helps.
-Srftech

advice to deal with esd not protected ics

1. I suggest you bond all the grounds first.

2. The bonder you referenced is a ball bonder and as such extreme caution must be taken on setting your reset and sebsequesnt EFO height. Your EFO is the greatest risk I see to your device. You might consider wedge bonding which will also give you a more reliable bond to thin plated gold which is typical on PCB's

microbill

There could be two ESD failure modes with wire bonding: 1) Machine Model (MM)where the bonding tool carries static charges and discharges to the die or 2) Charged Device Model (CDM) or in this case some call it Charged Board Model (CBM) where the die or the PC board (plus the insultive chuck if used) carry carges and discharge to the bonding tool/wire at the first bond.

To bond safely, you need to make sure that the bonding tool and bond wire are grounded to prevent the MM problem. To prevent CDM or CBM, there are several things you need to do:
1. Use grounded conductive chuck or board holder.
2. Make sure that the die/PCB are neutralized of all static charges. This is done by exposing the PCB to a gentle stream of balanced ionized air. If yo do thermal-sonic bonding and worry about the cooling affect of the ionizer, use radioactive type.
3. Do a stitch bond on the ground line of the PCB first and then if possible, do the samething on the die. Grounding to ground stitch bond should get rid of most of the stored charge on the PCB and die. If you can not to the stitch bond on the die, bond ground pad first.
4. Use copper tape to short out all the pins of the chip during the rest of the process, if possible.

Of course, basic ESD handling of the die and bonded PCB must be observed.

I know that this inofrmation may be too late for you, but I hope it would help.

Regards,
Wayne Tan