Programmable Gain Amplifier

switched capacitor programmable gain amplifier

Dear All

I am presently designing a switched capacitor based PGA. The gain is set using a variable feedback capacitor. Many capacitors are connected between the op-amp input and the output. Suitable feedback capacitance is selected using switches between the capacitors and the op-amp output.

Please let me know your opinion about how to deal with the unused capacitors. The switches connected to them are turned OFF. One end of the cap is connected to the op-amp input and the other end is floating. Can this contribute to noise? Should I connect the floating end to a reference voltage?

Thank You
Sachin

switching cap pga amplifier

Dear sachinagg77

In my opinion, if you keep any node floating, it will definitely pick up noise from other sources that are have parasitic capacitor to that node. The node of unused capacitors is the bottom plate. So best thing is to drive this node, or connect it to some reference voltage.

Another thing to consider here is, since you are keeping the other terminal of capacitor connected to the virtual ground node of the OTA, the feed back factor will go worse and the gain error will increase. So you have to make sure that your OTA provides sufficient gain to take care of that, or try to isolate it again with switches.
Though adding a switch at that point may not be a good idea when you take charge injection into consideration. But if you are not changing your gain of OTA every cycle by switching in and out the capacitors, then it might work.

Please share your results with you circuit when you are done

Dear Prince

Thanks for your detailed explanation.

I understand that any high impedance node will pick up noise. The circuit is fully differential. Do you think it will help reduce the impact? I searched but was unable to find any technical paper that refers to the unused capacitor connections.

Thanks for mentioning the "change in beta". Besides gain error, another major impact of beta change in the increased gain-bandwidth product requirement for the op-amp. This PGA has gain ranging from 0dB to 12dB with 3db steps. The accuracy requirements in 12 bits. Therefore, the capacitors are relatively large => large change in beta if unused large caps connected to a reference.

Regarding your suggestion about adding another switch on the other side of the capacitor, the gain of the circuit is not changed every cycle. But, I think that the on-resistance of the switch might pose a problem for this application. It impacts the beta and might raise stability issues. This design works at 50MHz. What do you think?

Looking forward for your further comments.

With Regards

Sachin

Though your circuit is differential, it will be very difficult to make sure in the layout to have equal noise sources for both high impedance nodes. Hence it is generally recommended to take precautions in the design itself.

As long as you allow your circuit to settle with 9τ or more, the resistor will have no role to play. The parasitic cap added by switch will be much smaller than the that of cap of input MOS pair, hence don't worry about that cap on virtual node.
Though it may introduce a pole (due to parasitic cap and resistor) but it will be at very high frequency.
I don't foresee any stability issues as of now, but you generally get a clear picture once you simulate.