Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Comparator design - input, Vin & Vref, specific gain

Status
Not open for further replies.
M

Monady

Advanced Member level 4
Full Member level 1
Joined
Dec 1, 2008
Messages
109
Helped
12
Reputation
24
Reaction score
3
Trophy points
1,298
Activity points
2,151
Comparator design

i heard that if we use of open loop opamp as a comparator, it's not needed to use of input common mode for opamp inputs(without dc biasing) and only apply Vin & Vref.
is it true?
i think that if we need specific resolution, we must have specific gain.if we don't use of Vcmi, transistors will not be in saturation regime, thus we have not desired gain.
i don't know that which of these reasons is true.
 

Re: Comparator design

Theoretically, yes, if the input stages gets saturated by DC, then the whole mechanism collapse.
In practice, comparator are not totally the same as opamp in that
we often add differential type cross-coupled latch stage before digital output buffer. And even in cases where input differential pair is not really in linear region we can get correct result since with cross coupled latch, never two output (positive / negative) shall both stay at same logic level (high / low).
Only thing to watch out is how much time it takes to resolve the difference of input signal level difference when it comes to small as mV.

Hope it helps,
 

    M

    Monady

    Points: 2
    Helpful Answer Positive Rating
Comparator design

thnx for your reply.but if we don't use of dc biasing voltage for input transistors,is it possible to reach a specific gain that is mandatory for desired resolution?for example we must have a gain=1800 for Vin(min)=1mv in 0.18u technology(Vdd=1.8v).
 

Re: Comparator design

With above saying multi-stage, gain of a few thousands is not problem.
Another limiting factor of resolution is offset voltage (matching of input MOS).
We need to use size enough to make offset statistically small enough (say, less than 1mV).

Good Luck,
 

    M

    Monady

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top