LVS error in ESD design

esd3dmy layout

I am designing ESD Vdd/Vss protection for core voltage and during LVS I get error because LVS extract esd25_diode( it's some ideal diode with giant current). I use two layers: ESD implant which need to make source and drain diffusions larger and one which block silicide. If I remove any of them, LVS is ok. I don't understand the reason. I'd appriciate it, if you helped me. I use tsmc013

tsmc esd3dmy layout

So its been a while since I looked in depth at TSMC013, but if I am not mistaken the ESD implant layers are very specific in their use. As the user you do not define the ESD implant mask, rather you place or do not place their ESD3DMY(?) layer. The implant itself is derived by logical mask operations during fracture.

When you state you are using two layers I am uncertain which layers you mean, but I assume the ESD3DMY layer is what you refer to as implant and then the RPO layer for silicide blocking.

I think the core issue here is that these layers are for use with MOS devices.
These ESD layers are generally not to be used over the diode, even if that diode is used in the IO as ESD protection.

Short answer, only place the ESD layer over output MOS devices, not diodes, same with RPO. esd25_diode I believe does not use the layer, nor should it, which is why your having LVS problems.

I hope this helps (its been 2 years since I looked extensively at that process). :|

lvs error parasitic diode

I placed ESD3DMY on core voltage MOS. I was confused because of some controdictions.

1. In Layout Guidlines for Latch-up and I/O ESD is written "An ESD implant mask is required in Vdd/Vss protection devices for 1.0V or 1.2V circuits. A logic operation generate the ESD implant mask. This logic operation requires an ESD dummy layer(ESD3DMY) in the layout". From the other hand, in TSMC usage description file is written "ESD3DMY - Layer for DRC, LVS and ESD implantation mask generation. Use ESD3DMY to cover high voltage tolerant 3.3V NMOS I/O devices"

2. If I look into Layout Guidlines for Latch-up and I/O ESD I can read "unsilicided MOS is not allowed as the power-pin ESD protection device for thin oxide circuits". But after two pages there is a table (see attached one) with RPO(silicide blocked layer) Layout. In addition And they write that there is need RPO and ESD1DMY(layer for check RPO rule check in ESD device)

esd diode stack darlington

yxo said:

I placed ESD3DMY on core voltage MOS. I was confused because of some controdictions.
...
2. If I look into Layout Guidlines for Latch-up and I/O ESD I can read "unsilicided MOS is not allowed as the power-pin ESD protection device for thin oxide circuits".

Click to expand...

AFAIR this is a typo. Should read: "silicided MOS is not allowed ..., because the high poly resistance is necessary for the protection.[/quote]

But if I combine ESD3DMY and RPO layers on 1V MOS I get an error during LVS

yxo said:

But if I combine ESD3DMY and RPO layers on 1V MOS I get an error during LVS

Click to expand...

Did you already try RPO only?

Use ESD3DMY to cover high voltage tolerant 3.3V NMOS I/O devices

Click to expand...

Your esd25_diode doesn't belong to this category.

Yes. When I place RPO only, everything is ok. As for diode, sorry, I didn't explain it clear. I meant that ASSURA finds out, detected (I saw it in the log file) and tried to extract it from layout . It is odd, because I think this diode only for simulation as it doesn't have layout view and its CV curve has megaamperes in forward bias(I found this diode in the tsmc library and made some simulation)

yxo said:

Yes. When I place RPO only, everything is ok. As for diode, sorry, I didn't explain it clear. I meant that ASSURA finds out, detected (I saw it in the log file) and tried to extract it from layout . It is odd, because I think this diode only for simulation ...

Click to expand...

No, it is for additional ESD protection.

yxo said:

... as it doesn't have layout view ...

Click to expand...

It must have a layout view - otherwise it can't help for ESD protection javascript:emoticon('')

yxo said:

... and its CV curve has megaamperes in forward bias(I found this diode in the tsmc library and made some simulation)

Click to expand...

That's why it is a rather big and powerful device for ESD protection javascript:emoticon('')

Added after 3 minutes:

yxo said:

Yes. When I place RPO only, everything is ok. As for diode, sorry, I didn't explain it clear. I meant that ASSURA finds out, detected (I saw it in the log file) and tried to extract it from layout . It is odd, because I think this diode only for simulation ...

Click to expand...

No, it is for additional ESD protection.

yxo said:

... as it doesn't have layout view ...

Click to expand...

It must have a layout view - otherwise it can't help for ESD protection :-((

yxo said:

... and its CV curve has megaamperes in forward bias(I found this diode in the tsmc library and made some simulation)

Click to expand...

That's why it is a rather big and powerful device for ESD protection ;-)

PostPosted: 04 Dec 2008 11:04 Post subject: Re: LVS error in ESD design
yxo wrote:
I placed ESD3DMY on core voltage MOS. I was confused because of some controdictions.
...
2. If I look into Layout Guidlines for Latch-up and I/O ESD I can read "unsilicided MOS is not allowed as the power-pin ESD protection device for thin oxide circuits".

erikl wrote:
AFAIR this is a typo. Should read: "silicided MOS is not allowed ..., because the high poly resistance is necessary for the protection.

Click to expand...

Be careful here guys...the implant and mask placement depends a lot on what type of ESD protection you are using. TSMC since 0.18 and below almost always uses active clamps for LV protection of power pins and power domains. These active clamps are not expected to go into snapback during a normal ESD event and as such should not have the RPO layer (silicide blocking layer). It is not a typo, rather the chart is referencing an earlier era and I feel needs to be updated. Power clamps on the 3.3V domains however are snapback based and therefore require the RPO layers so that they do not burn out.

Also, the goal of silicide blocking is not to increase the poly resistance (though that happens), but rather the drain and source resistance so that during snapback, current crowding and hot-spots do not form along the edge of the gate, causing the device to burn out.

But note, that if a 1V device is used on an output, it will definitely need the RPO layer and should be designed to withstand snapback.

What you will find is that depending on the usage of the device (output buffer, snapback clamp, active clamp, etc), this usage will dictate what the appropriate layers are.

So MOS output buffers will always need ESD3DMY and RPO layers; 3.3V and higher tolerant power clamps that are snapback based will always need ESD3DMY and RPO layers. LV devices that are output buffers will need RPO layers (I am still not certain if they need ESD3DMY as that serves a different purpose, you will need to contact TSMC to get that verified, or examine a 1V GPIO from their library, but I do not think you want to use ESD3DMY for 1V MOS outputs)....but their 1V power clamps, which should be active clamps by design should NOT have an RPO and ESD3DMY layers.
You should not be using snapback based clamps for your LV protection.

One comment on the huge diode current. Do not trust any of the TSMC diode models in forward bias. These diodes are models for accuracy under reverse bias conditions. Forward bias...they are simply ideal diode models and these megaamperes is not because its an ESD device but because it is not realistic. It is very hard to build an accurate diode model in both forward and reverse bias conditions. DO NOT TRUST FORWARD BIASED DIODE MODELS, ESPECIALLY FOR ESD Level currents unless you have verified that the foundry went to special lengths to build an accurate model...but I will tell you they never do. The only exception is occasionally an analog diode that is modeled well under forward biased is offered...but this is an exception and is not the norm.
Most diodes models are only accurate to a few hundred mV (say no higher than 0.5V) in forward condition.

About low voltage clamps is really interesting. Thanks.However, I do not understand it clearly.Why are they do not go into snapback. As far as I see it, during ESD event the voltage on CoreVDD will be high and NPN appear.
And the second question, I wonder, why output transistor must have unsilicided drains? Do they participate in ESD protection?

Hi yxo,
So here is the difference: in order for an nmos to snapback, the voltage on the drain must be high enough to trigger avalanche and eventually the NPN. This can be a very high voltage (3.3V device in 0.18um will snapback in a range of 10-13V on average etc....I will not discuss low voltage triggered snapback clamps here)

When you design an active clamp, your clamps are meant to operate in normal MOS conduction, so, say you are using a large network of nmos clamps, the idea is that they will conduct , for example, an ideal 1.3A 2kV HBM pulse at Vcc nominal or lower, and that they will do so while acting as a normal MOS device/switch.

Example case study of the top of my head:
If your VCC nominal is 3.3V and your snapback voltage to trigger the NPN is 8V, and if your VCC ESD clamps can handle 1.3A while holding the voltage at ~2.9V under normal MOS conduction.....
When your device experiences this ideal HBM pulse...your active clamp will not let the voltage get much high than 3V. Therefore the devices in the clamp, and on the Vcc domain, never see a drain voltage high enough to trigger snapback in the core. This is one of the beauties of active clamp design.

The reason output devices almost always need unsilicide drains is two fold...it used to be that the output drivers were the exclusive ESD protection for an IO. Nowadays we see a lot more discrete ESD structures such as SCR's or my favorite, Diodes and active clamps. But even these have parasitic resistances and added paths for the ESD current, as such the output MOS devices are always at higher risk for experiencing Voltage levels capable of triggering snapback.

Does this make sense?

Yeah, I see it...About clamps, it means that the string of Diodes can holds the voltage (number_of_diodes * Vth) and works as a clamp. Is it right?

Yes Diodes can be used as clamps, but be very careful, diode stacks are not consistent in their operation during an ESD event.
A few things to consider, stacked diodes have a darlington effect unless they are in an isolated well or SOI technology. Because in trurth, stacked diodes are always built in wells (example, nwells, assuming P substrate technology), and those wells have parasitic junctions to substrate so what you think is a string of diodes is really a string of bipolar devices.

Draw this out, a series of nwell P+ diodes in P-sub technology is actually not a diode but a series of PNP bipolars where your diode is formed between the emitter (P+ diffusion in Nwell) and the base (nwell), then the base of the first bipolar connects to the emitter of the next and so on. This is your stacked diode string. But all of them have their collectors shorted together (P+substrate). With each diode in the stack, you lose current to a collector, and thus less current for the next emitter-Base junction, ergo, effective Vth (really the drop across each diode) is not consistent for each diode. So number_of_diodes * Vth is not a good approximator, depending on your process ( it can be, but you need to understand the parasitic effects of your process).

Also, this stack is very temperature sensitive, because the diode junctions and the parasitic Bipolars are temperature sensitive, so the stacks current leakage and actual clamping voltage can vary dramatically.

Why is this a problem during an ESD event? Well it may not be but it is during normal operation. You design the diode stack to clamp at a voltage as close to VDD as possible, but then, you have to add lots of margin above VDD because you can't have your diode stack blowing up your chip during say a burn-in test or latch-up test, where the VDD's are raised a ltitle higher and temperatures increased. (I have seen diode stack clamps blow-up/melt burn-In board and power supplies because the clamps started to conduct loads of current during what was supposed to be normal operation.

Be very careful using Diode stacked based clamps, they have limitations and are known to cause problems, which is why they are not common in use as ESD Clamps..

thanks