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Why hold uncertainty is always less than setup uncertainty?

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santoshl

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hold uncertainty

Hi,
I have seen that hold uncertainty is always less than setup uncertainty. Shall we discuss for the possible reasons behind it??

Thanks in advance....
 

hold uncertanity

Yes. Setup time is the time taken by the data to reach the storage element. While hold time is the the time taken by the clock to reach the storage element.
Now if you see the internal architecture of the Flip Flop, you will find that the path is longer for the data ( have 3 logic element in the path) while for the clk path, we have only 1 inverter delay. So setup time is more than hold time.
Hope this answers your question.....
 

uncertainity and setup

setup checks are done at SS corner , where gate delays are slow
hold checks are done at FF corner , where gate delays are faster
hence clock skews at SS corner are bigger than at FF corner
 
setup time in ss corner

Guess the host is more concerned with the uncertainty than exact value?

Anyway...I am also curious about this. Also, if some1 can give insight of the mechanism of setup/hold time, it will be great.

@nd floor said something about data/clock to the storage element, I dont quite catch that...I have an impression that setup/hold time can be measured by these parameters of the latches...ofc I don't know how to measure those of the latches ^^
 

hold time always less than setup time

I think they have no relationship.

at synthesis stage, more concern on reduce path timing, so setup uncertainty is more important to add margin to design.

hold is easy fix, so less important,

when do timing check, you should set a more consertive hold uncertainty .



and SS clock skew maybe not larger than FF corner.
 

setup and hold uncertainty

I think it has the relationship with the nature of setup/hold check.

Let's take a simple example, maybe you set the uncertainty include the clock skew and cycle to cycle jitter, for setup check , the tool will check the data arrival time in the next cycle cycle.
But for Hold check ,tool will check the data arrival time in the current cycle ,so ,there is no reason to set the hold uncertainty include the cycle to cycle jitter,becasue it will worse the timing result .

That's why hold uncertainty always less than setup uncertainty.
 

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    chakri92

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Re: Why hold uncertainty is always less than setup uncertain

hi ,

my 2 cents,

what i could think of is

setup uncertainity: Having a higher number , optimizes the path, with better optimization techniques, increases the circuit speed, reduces cell count...

where as in the contrary

hold uncertainity: having more value , means more cells to placed which inturn increases area, which is costly.
so i believe this is used on need basis.

hope i made sense

happy designing,

chip design made easy
https://www.vlsichipdesign.com
 

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