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problem in uart receiver code............

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mkanimozhivlsi

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uart receiver

Hi,
This is my uart receiver code


library ieee;
use ieee.std_logic_1164.all;


Entity uart_rx is
Port(
bclk,rst: in std_logic;
rxd: in std_logic;
data_rdy: out std_logic;
data_out : out std_logic_vector(7 downto 0));
End entity;

Architecture arch_uart_rx of uart_rx is

type state is (idel,start_bit,bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,stop_bit);
signal ps,ns: state;
signal data_buff: std_logic_vector(9 downto 0);

begin

process(bclk,rst)
begin
if(rst='0') then
ps<=idel;
data_out<=(others=>'0');
elsif(bclk='1' and bclk'event) then
ps<=ns;
end if;
end process;


process(ps,rxd)
begin
case (ps) is

when idel =>
data_out<=(others=>'0');
data_rdy<='0';

if(rxd='1') then
ns<=start_bit;
else
ns<=idel;
end if;

when start_bit =>
data_out<=(others=>'0');
data_buff(0)<=rxd;
data_rdy<='0';
if(rxd='0') then
ns<=bit0;
else
ns<=idel;
end if;

when bit0 =>

data_out<=(others=>'0');
data_rdy<='0';
data_buff(1)<=rxd;
ns<=bit1;

when bit1 =>

data_out<=(others=>'0');
data_rdy<='0';
data_buff(2)<=rxd;
ns<=bit2;

when bit2 =>
data_out<=(others=>'0');
data_rdy<='0';
data_buff(3)<=rxd;
ns<=bit3;

when bit3 =>
data_out<=(others=>'0');
data_rdy<='0';
data_buff(4)<=rxd;
ns<=bit4;

when bit4 =>
data_out<=(others=>'0');
data_rdy<='0';
data_buff(5)<=rxd;
ns<=bit5;

when bit5 =>
data_out<=(others=>'0');
data_rdy<='0';
data_buff(6)<=rxd;
ns<=bit6;

when bit6 =>
data_out<=(others=>'0');
data_rdy<='0';
data_buff(7)<=rxd;
ns<=bit7;

when bit7 =>
data_out<=(others=>'0');
data_rdy<='0';
data_buff(8)<=rxd;
ns<=stop_bit;

when stop_bit=>

data_buff(9)<=rxd;
if(rxd='1')then
data_out<=data_buff(8 downto 1);
data_rdy<='1';
ns<=idel;
else
data_out<=(others=>'0');
end if;

end case;
end process;
end architecture;


i don't know what is wrong in this code, it's working properly , but it will not output properly wat the input received, it displays "X" dor values received as logical 1, for logical 0 it's displaying correctly, i don't y, please some one help me to solve this issue

regards
kanimozhi.m
 

have you simulated your code using ModelSim or ActiveHDL?

If not, then please simulate and debug your code...

Added after 1 minutes:

Maybe one hint:
what bit is sent first? What bit (MSB or LSB) is expected?
 

The error in your code is that two processes are driving "data_out" signal. You should move reset logic for "data_out" from the first process to the second, so that "data_out" will have only one driver.
 
Maybe one hint:
what bit is sent first? What bit (MSB or LSB) is expected?
 

Thank u ringo, now i m getting correct output

reagrds
kanimozhi.M
 

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