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Cadence design of PMOS amp of 40dB at 100MHz

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Srikant Rao

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Cadence

Hello
I am having trouble with this question
Design a PMOS load common source amplifier to provide a gain of 40db and unity gain frequency of 100 MHz
I have tried a combination of gm/Id and hit and trial and am unable to meet both the constraints.
 

Cadence

Why do you think it is posible? 40 dB is too high gain for CS amplifier. Gain = gmi(r01+ r02) r01,r02 small signal resistance of input transistor and load. I think even you have very small current you can't achive 40dB
 
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