Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Why PMOS and NMOS are sized equally in a Transmission Gates

Status
Not open for further replies.
R

ramana459

Junior Member level 3
Junior Member level 3
Joined
Apr 1, 2008
Messages
27
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,436
beta ratio of pmos to nmos

Actually NMOS width is 2 times less than PMOS width in CMOS logic designs,
but in one article I observed PMOS and NMOS are sized equally in a Transmission Gates..........
is it correct???????????
is it possible only in transmission gates or any other circuits?????


Ramana
 

transmission gates-asic

Sometimes we use the same size of PMOS and NMOS for easy layout. Besides, the junction capacitance is another consideration,too.
 
why pmos size is 2times nmos

in layout purpose its ok .... but will it defect on speed of operation, because mobility of pmos is less than the nmos.
 

why pmos and nmos are sized equally in gate

If you vary the PMOS to NMOS actice area ratio for the constraint:

Fixed S/D-Cap on one side or sum of both sides. Then search for the best PMOS to NMOS ratio which gives the lowest maximum Ron over the input voltage range.

The ratio should be similar to the logic ratio.
 

ratio of pmos nmos width =2

The reason you would find a beta ratio equal to 1 in some instances is because, when the transmission gate is turned-on, both the pmos and nmos are turned on and are in parallel. Even though only the pfet is good at passing '1' and nfet is good at passing '0', they do pass the opposite logic level weakly. So, together the average resistance is lower than having only one FET on. So, you don't really need a beta=2 like in an inverter but something like 1.5 or 1 is sufficient.
 
nmos beta

May be the sizes are equal bcoz when switch gets off the holes in a PMOS channel and electrons in a NMOS are cancels each other and overall charge injection reduces.

Thanking You.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top