Microprocessor design factors

For a certain set of instructions my microprocessor has to execute and take a lot of backward branches (e.g. the BEQ instruction in a loop is "taken" when it evaluates to true). Anyone knows how I can use this info to optimize my MP?

Thanks.

Opel_Corsa said:

For a certain set of instructions my microprocessor has to execute and take a lot of backward branches (e.g. the BEQ instruction in a loop is "taken" when it evaluates to true). Anyone knows how I can use this info to optimize my MP?

Thanks.

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Is your question that you are designing a microprocessor and want to know how to optimize its design? Or are you trying to optimize code for a particular microprocessor?

In the first case - if your processor has an instruction pipeline where you prefetch instructions cycles ahead of executing them, then performing some kind of branch prediction may save you cycles. The simplest possible prediction is the one you describe - if you branch back, you predict the branch is taken, for a branch forward you predict not taken. The processor prefetches either from the branch
target address (if predicted taken) or from the next instruction (if predicted not taken). Of course, you still have to evaluate the condition code when the branch instruction executes and check that the guess was correct. If the guess was incorrect, then you have to flush the prefetched instructions and fetch from the correct location.

This simple kind of prediction is usually correct about 60% of the time, so usually gives some performance uplift, but you need more complicated branch prediction schemes to get better prediction rates.

If you are simply trying to optimize assembly code, then you might look at techniques like loop unrolling.

Thanks alot! Yes I was looking for ways to optimize the design of the MP. Now what if we know that for a certain set of instructions the value read from an integer register is most of the time 0? How might one use this knowledge to optimize the design of the MP?

Thanks again.